參數(shù)資料
型號(hào)： X40020S14IZ-B
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝： 0.150 INCH, ROHS COMPLIANT, SOIC-14
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 360K
代理商： X40020S14IZ-B
14
FN8112.1
May 17, 2006
Figure 13. Slave Address, Word Address, and Data Bytes
Word Address
The word address is either supplied by the master or
obtained from an internal counter.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for
t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
General Purpose Memory
Control Register
Fault Detection Register
1
1
1
0
0
0
1
1
1
0
1
1
A8 R/W
1
0
Word Address
Slave Byte
0
0
0
0
0
0
R/W
R/W
General Purpose Memory
Control Register
Fault Detection Register
A7
1
1
A6
1
1
A5
1
1
A4
1
1
A1
1
1
A0
1
1
A3
1
1
A2
1
1
X40020, 40021
相關(guān)PDF資料
PDF描述
X40020S14Z-A Dual Voltage Monitor with Intergrated CPU Supervisor
X40020S14Z-B Dual Voltage Monitor with Intergrated CPU Supervisor
X40020V14IZ-A Dual Voltage Monitor with Intergrated CPU Supervisor
X40020V14IZ-B Dual Voltage Monitor with Intergrated CPU Supervisor
X40020V14Z-A Dual Voltage Monitor with Intergrated CPU Supervisor
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