參數(shù)資料
型號(hào): X28HC64JZ-70
廠商: INTERSIL CORP
元件分類: DRAM
英文描述: 5 Volt, Byte Alterable EEPROM
中文描述: 8K X 8 EEPROM 5V, 70 ns, PQCC32
封裝: ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32
文件頁(yè)數(shù): 9/17頁(yè)
文件大?。?/td> 265K
代理商: X28HC64JZ-70
9
FN8109.1
June 7, 2006
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
Figure 7. Write Sequence for Software
Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically dis-
able further writes unless another command is issued
to deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
Note:
Once initiated, the sequence of write operations
should not be interrupted.
CE
WE
(V
CC
)
Write
Protected
V
CC
0V
Data
ADDR
AAA
1555
55
0AAA
A0
1555
t
BLC MAX
Writes
OK
Byte
or
Page
t
WC
Write Last
Byte to
Last Address
Write Data XX
to Any
Address
Write Data A0
to Address
1555
Write Data 55
to Address
0AAA
Write Data AA
to Address
1555
After t
Re-Enters Data
Protected State
Optional
Byte/Page
Load Operation
Byte/Page
Load Enabled
X28HC64
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