
X28C64
15
DATA
Polling Timing Diagram
(10)
3853 FHD F09
ADDRESS
AN
DIN=X
DOUT=X
DOUT=X
tWC
tOEH
tOES
AN
AN
CE
WE
OE
I/O7
tDW
Toggle Bit Timing Diagram
(10)
3853 FHD F10
CE
OE
WE
I/O6
tOES
tDW
tWC
tOEH
HIGH Z
*
*
* Starting and ending state of I/O6 will vary, depending upon actual tWC.
Note:
(10) Polling operations are by definition read cycles and are therefore subject to read cycle timings.