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參數(shù)資料
| 型號： | X24C01SMG-3.5 |
| 廠商： | IC MICROSYSTEMS SDN BHD |
| 元件分類： | DRAM |
| 英文描述： | Serial E2PROM |
| 中文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 289K |
| 代理商： | X24C01SMG-3.5 |
10
X24C01
WRITE CYCLE LIMITS
Symbol
Parameter
Min.
Typ.
(5)
Max.
Units
t
WR(6)
Write Cycle Time
5
10
ms
3837 PGM T08
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the X24C01
Write Cycle Timing
bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its word address.
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
X24C01
ADDRESS
SCL
3837 FHD F05
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
SYMBOL TABLE
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
OUTPUTS
INPUTS
WAVEFORM
3837 FHD F15
120
100
80
40
60
20
20
40
60
80100120
0
0
BUS CAPACITANCE (pF)
MIN.
RESISTANCE
MAX.
RESISTANCE
RMAX
=
CBUS
tR
RMIN
=
IOL MIN
VCC MAX
=2.6K
Ο
Notes:
(5) Typical values are for T
A
= 25
°
C and nominal supply voltage (5V).
(6) t
WR
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
R
Ο
)
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| X24C02 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
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| X24C02BM | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
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