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參數資料
| 型號： | X24C01APMG-3.5 |
| 廠商： | IC MICROSYSTEMS SDN BHD |
| 元件分類： | DRAM |
| 英文描述： | Serial E2PROM |
| 中文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-8 |
| 文件頁數： | 7/13頁 |
| 文件大小： | 285K |
| 代理商： | X24C01APMG-3.5 |
X24C01A
7
Sequential Read
Sequential Read can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C01A continues to
output data for each acknowledge received. The read
operation is terminated by the master, by not responding with
an acknowledge and by issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing the
entire memory contents to be serially read during
one operation. At the end of the address space (address 127),
the counter “rolls over” to address 0 and the
X24C01A continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowledge
and data transfer sequence.
Figure 9. Sequential Read
Figure 10. Typical System Configuration
3841 FHD F14
3841 FHD F15
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
V
CC
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C01A
SLAVE
ADDRESS
A
C
K
A
C
K
DATA n+x
S
T
O
P
P
DATA n
A
C
K
DATA n+1
A
C
K
DATA n+2
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相關代理商/技術參數 |
參數描述 |
|---|---|
| X24C01AS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-SM-1K CMOS SER EEPROM |
| X24C01AS-3.5C7000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| X24C01AS8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24C01AS8-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| X24C01AS8-3 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
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