參數(shù)資料
型號(hào): X24645SIG
廠商: IC MICROSYSTEMS SDN BHD
元件分類(lèi): DRAM
英文描述: Advanced 2-Wire Serial E2PROM with Block LockTM Protection
中文描述: 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14
封裝: ROHS COMPLIANT, PLASTIC, SOIC-14
文件頁(yè)數(shù): 12/18頁(yè)
文件大?。?/td> 331K
代理商: X24645SIG
X24645
12
A.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read
& Write Cycle Limits
2783 FRM T09.2
POWER-UP TIMING
(4)
2783 FRM T10
Notes:
(4)t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically
sampled and not 100% tested.
Symbol
Parameter
Min.
Max.
Units
f
SCL
SCL Clock Frequency
0
100
KHz
T
I
Noise Suppression Time
Constant at SCL, SDA Inputs
100
ns
t
AA
SCL LOW to SDA Data Out Valid
0.3
3.5
s
t
BUF
Time the Bus Must Be Free Before a
New Transmission Can Start
4.7
s
t
HD:STA
Start Condition Hold Time
4
s
t
LOW
Clock LOW Period
4.7
s
t
HIGH
Clock HIGH Period
4
s
t
SU:STA
Start Condition Setup Time (for
a Repeated Start Condition)
4.7
s
t
HD:DAT
Data In Hold Time
0
s
t
SU:DAT
Data In Setup Time
250
ns
t
R
SDA and SCL Rise Time
1
s
t
F
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
s
t
DH
Data Out Hold Time
300
ns
Symbol
Parameter
Max.
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
5
ms
A.C. CONDITIONS OF TEST
2783 FRM T08
Input Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input Rise and
Fall Times
10ns
Input and Output
Timing Levels
V
CC
X 0.5
EQUIVALENT A.C. LOAD CIRCUIT
2783 ILL F16.1
5V
1.53K
Ο
100pF
OUTPUT
相關(guān)PDF資料
PDF描述
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