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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | X1227V8IZ-2.7 |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 24/28闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC RTC/CAL/CPU SUP EE 8-TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 100 |
| 椤炲瀷锛� | 鏅�(sh铆)閻�/鏃ユ |
| 鐗归粸(di菐n)锛� | 璀﹀牨(b脿o)鍣�锛岄枏骞达紝鐩�(ji膩n)鎺у櫒锛岀洠(ji膩n)瑕栬▓(j矛)鏅�(sh铆)鍣� |
| 鏅�(sh铆)闁撴牸寮忥細 | HH:MM:SS锛�12/24 灏忔檪(sh铆)锛� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | YY-MM-DD-dd |
| 鎺ュ彛锛� | I²C锛�2 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V |
| 闆诲 - 闆绘簮锛岄浕姹狅細 | 1.8 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-TSSOP |
| 鍖呰锛� | 绠′欢 |
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5
FN8099.2
May 8, 2006
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10)VSDA = GND or VCC, VSCL = GND or VCC, VRESET = GND or VCC
(11)IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12)
IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25掳C).
(15)Typical values are for TA = 25掳C
Capacitance TA = 25掳C, f = 1.0 MHz, VCC = 5V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Figure 1. Standard Output Load for testing the device with VCC = 5.0V
Symbol
Parameter
Max.
Units
Test Conditions
COUT(1)
Output Capacitance (SDA, RESET)10
pF
VOUT = 0V
CIN(1)
Input Capacitance (SCL)
10
pF
VIN = 0V
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
VCC x 0.5
Output Load
Standard Output Load
SDA
1533
惟
100pF
5.0V
For VOL= 0.4V
and IOL = 3 mA
Equivalent AC Output Load Circuit for VCC = 5V
X1227
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| X1227V8-2.7 | IC RTC/CAL/CPU SUP EE 8-TSSOP |
| MCP4252-104E/UN | IC POT DGTL 100K 257TAPS 10-MSOP |
| MCP4251-104E/SL | IC DGTL POT 100K 2CH 14SOIC |
| MCP4251-104E/ST | IC DGTL POT DL 100K 2CH 14-TSSOP |
| MS3106A32-17S | CONN PLUG 4POS STRAIGHT W/SCKT |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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