The bit is set regardless of whether VCC or V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� X1227S8Z-2.7
寤犲晢锛� Intersil
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 5/28闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC RTC/CAL/CPU SUP EE 8-SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 100
椤炲瀷锛� 鏅�(sh铆)閻�/鏃ユ
鐗归粸(di菐n)锛� 璀﹀牨(b脿o)鍣�锛岄枏骞�锛岀洠(ji膩n)鎺у櫒锛岀洠(ji膩n)瑕栬▓(j矛)鏅�(sh铆)鍣�
鏅�(sh铆)闁撴牸寮忥細 HH:MM:SS锛�12/24 灏忔檪(sh铆)锛�
鏁�(sh霉)鎿�(j霉)鏍煎紡锛� YY-MM-DD-dd
鎺ュ彛锛� I²C锛�2 绶氫覆鍙�
闆绘簮闆诲锛� 2.7 V ~ 5.5 V
闆诲 - 闆绘簮锛岄浕姹狅細 1.8 V ~ 5.5 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 绠′欢
13
FN8099.2
May 8, 2006
The bit is set regardless of whether VCC or VBACK is
applied first. The loss of only one of the supplies does
not set the RTCF bit to 鈥�1鈥�. On power-up after a total
power failure, all registers are set to their default
states and the clock will not increment until at least
one byte is written to the clock register. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to 鈥�0鈥� (writing one byte is suffi-
cient).
Unused Bits:
This device does not use bits 3 or 4 in the SR, but must
have a zero in these bit positions. The Data Byte output
during a SR read will contain zeros in these bit locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits鈥擝P2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
Watchdog Timer Control Bits鈥擶D1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Table 4. Watchdog Timer Time-Out Options
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) 鈥� DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
BP2
BP1
BP0
Protected Addresses
X1227
Array Lock
0
None (Default)
None
00
1
180h - 1FFh
Upper 1/4
01
0
100h - 1FFh
Upper 1/2
01
1
000h - 1FFh
Full Array
10
0
000h - 03Fh
First Page
10
1
000h - 07Fh
First 2 pgs
11
0
000h - 0FFh
First 4 pgs
11
1
000h - 1FFh
First 8 pgs
WD1 WD0
Watchdog Time-Out Period
0
1.75 seconds
0
1
750 milliseconds
1
0
250 milliseconds
1
Disabled (default)
DTR Register
Estimated frequency
PPM
DTR2
DTR1
DTR0
00
0
0 (Default)
01
0
+10
00
1
+20
01
1
+30
10
0
11
0
-10
10
1
-20
11
1
-30
X1227
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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