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    參數(shù)資料
    型號(hào): X1227S8
    廠商: Intersil
    文件頁(yè)數(shù): 7/28頁(yè)
    文件大?。?/td> 0K
    描述: IC RTC CPU SUP WDT 4K EE 8-SOIC
    標(biāo)準(zhǔn)包裝: 100
    類型: 時(shí)鐘/日歷
    特點(diǎn): 警報(bào)器,閏年,監(jiān)控器,監(jiān)視計(jì)時(shí)器
    時(shí)間格式: HH:MM:SS(12/24 小時(shí))
    數(shù)據(jù)格式: YY-MM-DD-dd
    接口: I²C,2 線串口
    電源電壓: 4.5 V ~ 5.5 V
    電壓 - 電源,電池: 1.8 V ~ 5.5 V
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
    供應(yīng)商設(shè)備封裝: 8-SOIC
    包裝: 管件
    15
    FN8099.2
    May 8, 2006
    POWER-ON RESET
    Application of power to the X1227 activates a Power-
    on Reset Circuit that pulls the RESET pin active. This
    signal provides several benefits.
    – It prevents the system microprocessor from starting
    to operate with insufficient voltage.
    – It prevents the processor from operating prior to sta-
    bilization of the oscillator.
    – It allows time for an FPGA to download its configura-
    tion prior to initialization of the circuit.
    – It prevents communication to the EEPROM, greatly
    reducing the likelihood of data corruption on power-up.
    When VCC exceeds the device VTRIP threshold value
    for typically 250ms the circuit releases RESET, allow-
    ing the system to begin operation. Recommended
    slew rate is between 0.2V/ms and 50V/ms.
    WATCHDOG TIMER OPERATION
    The watchdog timer is selectable. By writing a value to
    WD1 and WD0, the watchdog timer can be set to 3 dif-
    ferent time out periods or off. When the Watchdog
    timer is set to off, the watchdog circuit is configured for
    low power operation.
    Watchdog Timer Restart
    The Watchdog Timer is started by a falling edge of
    SDA when the SCL line is high and followed by a stop
    bit. The start signal restarts the watchdog timer
    counter, resetting the period of the counter back to the
    maximum. If another start fails to be detected prior to
    the watchdog timer expiration, then the RESET pin
    becomes active. In the event that the start signal
    occurs during a reset time out period, the start will
    have no effect. When using a single START to refresh
    watchdog timer, a STOP bit should be followed to
    reset the device back to stand-by mode.
    LOW VOLTAGE RESET OPERATION
    When a power failure occurs, and the voltage to the
    part drops below a fixed vTRIP voltage, a reset pulse is
    issued to the host microcontroller. The circuitry moni-
    tors the VCC line with a voltage comparator which
    senses a preset threshold voltage. Power-up and
    power-down waveforms are shown in Figure 5. The
    Low Voltage Reset circuit is to be designed so the
    RESET signal is valid down to 1.0V.
    When the low voltage reset signal is active, the operation
    of any in progress nonvolatile write cycle is unaffected,
    allowing a nonvolatile write to continue as long as possi-
    ble (down to the power-on reset voltage). The low volt-
    age reset signal, when active, terminates in progress
    communications to the device and prevents new com-
    mands, to reduce the likelihood of data corruption.
    Figure 4. Watchdog Restart/Time Out
    tRSP<tWDO
    tRST
    RESET
    SDA
    tRSP
    Note: All inputs are ignored during the active reset period (tRST).
    tRST
    SCL
    tRSP>tWDO
    Start
    Stop Start
    X1227
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