2
FN8098.3
May 8, 2006
PIN CONFIGURATION
Ordering Information
PART NUMBER
PART MARKING
VDD (V)
TEMP
RANGE (°C)
PACKAGE
PKG. DWG. #
X1226S8*
X1226
2.7 to 5.5
0 to 70
8 Ld SOIC (150 mil)
MDP0027
X1226S8Z* (Note)
X1226Z
0 to 70
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
X1226S8I*
X1226I
-40 to 85
8 Ld SOIC (150 mil)
MDP0027
X1226S8IZ* (Note)
X1226ZI
-40 to 85
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
X1226V8*
1226
0 to 70
8 Ld TSSOP (4.4mm)
M8.173
X1226V8Z* (Note)
1226Z
0 to 70
8 Ld TSSOP (4.4mm) (Pb-free)
M8.173
X1226V8I*
1226I
-40 to 85
8 Ld TSSOP (4.4mm)
M8.173
X1226V8IZ* (Note)
1226IZ
-40 to 85
8 Ld TSSOP (4.4mm) (Pb-free)
M8.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X1
X2
VBACK
VCC
PHZ/IRQ
SCL
SDA
VSS
1
2
3
4
7
8
6
5
8 LD TSSOP
X1
X2
VBACK
VCC
PHZ/IRQ
SCL
SDA
VSS
1
2
3
4
7
8
6
5
8 LD SOIC
X1226