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參數(shù)資料
| 型號： | X1209 |
| 英文描述： | Real Time Clock/Calendar with Event/Timestamp Detection & Alarms(帶有事件/時(shí)間標(biāo)記檢測與報(bào)警功能的實(shí)時(shí)時(shí)鐘/日歷) |
| 中文描述： | 實(shí)時(shí)時(shí)鐘/日歷的事件/時(shí)間戳檢測 |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 511K |
| 代理商： | X1209 |
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REV 3.0 2/11/04
www.xicor.com
Preliminary Information
X1209
WRITING OR READING TO THE CLOCK/CONTROL
REGISTERS
Changing any of the volatile bits of the clock/control
register requires the following steps:
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
volatile register values.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The WRTC bit enables or disables write capability
into the RTC Timing Registers. Upon initialization or
power up, the WRTC must be set to “1” to enable the
RTC. Upon the completion of a valid write (STOP),
the RTC starts counting.
– Writing and Reading capability is disable during bat-
tery backup mode.
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the CCR.
Upon receipt of each address byte, the X1209
responds with an acknowledge. After receiving both
address bytes the X1209 awaits the eight bits of data.
After receiving the 8 data bits, the X1209 again
responds with an acknowledge. The master then termi-
nates the transfer by generating a stop condition. The
X1209 then begins an internal write cycle of the data to
the nonvolatile memory. During the internal write cycle,
the device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 7.
Stop and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1209 resets itself without per-
forming the write. The contents of the array are not
affected.
Acknowledge Polling
Once the stop condition is issued to indicate the end of
the master’s byte load operation, the X1209 initiates
the internal nonvolatile write cycle. Acknowledge poll-
ing can begin immediately. To do this, the master
issues a start condition followed by the Slave Address
Byte for a write or read operation. If the X1209 is still
busy with the nonvolatile write cycle then no ACK will
be returned. When the X1209 has completed the write
operation, an ACK is returned and the host can pro-
ceed with the read or write operation. Refer to the flow
chart in Figure 9.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change dur-
ing the course of a read operation. In this device, the
time is latched by the read command (falling edge of
the clock on the ACK bit prior to RTC data output) into
a separate latch to avoid time changes during the read
operation. The clock continues to run. Alarms occur-
ring during a read are unaffected by the read opera-
tion.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second clock cycle” after
the stop bit is written. The RTC continues to update the
time while an RTC register write is in progress and the
RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes
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