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參數(shù)資料
| 型號： | WV3DG7266V10D1 |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, ZMA144 |
| 封裝： | SODIMM-144 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 231K |
| 代理商： | WV3DG7266V10D1 |
WV3DG7266V-D1
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
OPERATING AC PARAMETERS
Parameter
Symbol
775
10
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
tCC
7.5
1000
7.5
1000
10
1000
ns
1
CAS latency=2
7.5
10
CLK to valid output delay
CAS latency=3
tSAC
5.4
6
ns
1, 2
CAS latency=2
5.4
6
Output data hold time
CAS latency=3
tOH
333
ns
2
CAS latency=2
3
CLK high pulse width
tCH
2.5
3
ns
3
CLK low pulse width
tCL
2.5
3
ns
3
Input setup time
tSS
1.5
2
ns
3
Input hold time
tSH
0.8
1
ns
3
CLK to output in Low-Z
tSLZ
111
ns
2
CLK to outpu in Hi-Z
CAS latency=3
tSHZ
5.4
6
ns
CAS latency=2
5.4
6
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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