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參數(shù)資料
| 型號： | WS57LV291C-90T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | RATED & SCALED 0-50 AAC - YOKOGAWA RoHS Compliant: NA |
| 中文描述： | 高速3.3伏2K × 8的CMOS胎膜早破/ RPROM |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 47K |
| 代理商： | WS57LV291C-90T |
PRODUCT SELECTION GUIDE
PARAMETER
WS57LV291C-70
WS57LV291C-90
Address Access Time (Max)
CS to Output Valid Time (Max)
70 ns
20 ns
90 ns
30 ns
HIGH SPEED 3.3 VOLT 2K x 8 CMOS PROM/RPROM
KEY FEATURES
3.3 Volt ± 0.3 Volt V
CC
Fast Access Time
— t
ACC
= 70 ns
— t
CS
= 20 ns
Low Power Consumption
—
≤
25 mA I
CC
Available in 300 Mil "Skinny" DIP
Immune to Latch-up
— Up to 200 mA
ESD Protection Exceeds 2000V
GENERAL DESCRIPTION
The WS57LV291C is a High Performance 2K x 8 UV Erasable Re-Programmable Read Only Memory (RPROM).
This RPROM is manufactured using an advanced CMOS EPROM manufacturing process resulting in a very low
power die that affords exceptional speed capabilities with a 3.3 volt V
CC
supply. The WS57LV291C
is configured in the standard Bipolar PROM pinouts, the preferred and most common pinout for high speed PROMs
of 16K density.
Operating at 3.3 volts, the WS57LV291C dissipates a maximum of 25 mA under worst case conditions at maximum
speed (70 ns T
AA
). Typical I
CC
at 25°C is less than 20 milliamps.
The WS57LV291C is packaged in a space saving 300 mil windowed, hermetic DIP package.
WS57LV291C
PRELIMINARY
V
CC
A
8
A
9
A10
CS1/V
PP
CS2
CS3
O
7
O
6
O
5
O
4
O
3
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TOP VIEW
CERDIP
PIN CONFIGURATION
2-15
ROW
DECODER
EPROM ARRAY
16,384 BITS
COLUMN
DECODER
SENSE
AMPLIFIERS
8
CS2
CS3
OUTPUTS
CS1/V
PP
A0 - A4
COLUMN
ADDRESSES
A5 - A10
ROW
ADDRESSES
6
5
BLOCK DIAGRAM
Return to Main Menu
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