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參數(shù)資料
| 型號(hào)： | WS512K32BV-17G2CE |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 17 ns, CQFP68 |
| 封裝： | 22.40 X 22.40 MM, CERAMIC, QFP-68 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 332K |
| 代理商： | WS512K32BV-17G2CE |
WS512K32BV-XXXE
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specications without notice.
December, 1999
Rev. 2
AC TEST CIRCUIT
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 .
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Current Source
D.U.T.
Ceff = 50 pf
IOL
IOH
VZ
1.5V
(Bipolar Supply)
Current Source
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 2.5
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
AC CHARACTERISTICS
(VCC = 3.3V, TA = -40°C to +85°C)
Parameter
Symbol
-15*
-17
-20
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
15
17
20
ns
Address Access Time
tAA
15
17
20
ns
Output Hold from Address Change
tOH
00
0
ns
Chip Select Access Time
tACS
15
17
20
ns
Output Enable to Output Valid
tOE
7
8
10
ns
Chip Select to Output in Low Z
tCLZ1
22
2
ns
Output Enable to Output in Low Z
tOLZ1
00
0
ns
Chip Disable to Output in High Z
tCHZ1
7
8
10
ns
Output Disable to Output in High Z
tOHZ1
7
8
10
ns
AC CHARACTERISTICS
(VCC = 3.3V, TA = -40°C to +85°C)
Parameter
Symbol
-15*
-17
-20
Units
Write Cycle
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
15
17
20
ns
Chip Select to End of Write
tCW
10
12
14
ns
Address Valid to End of Write
tAW
10
12
14
ns
Data Valid to End of Write
tDW
8
9
10
ns
Write Pulse Width
tWP
12
14
ns
Address Setup Time
tAS
00
0
ns
Address Hold Time
tAH
00
0
ns
Output Active from End of Write
tOW1
23
3
ns
Write Enable to Output in High Z
tWHZ1
88
9
ns
Data Hold Time
tDH
00
0
ns
1. This parameter is guaranteed by design but not tested.
*Advanced information.
1. This parameter is guaranteed by design but not tested.
*Advanced information.
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