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參數(shù)資料
| 型號(hào)： | WS27C010L-20DMB |
| 元件分類： | PROM |
| 英文描述： | 128K X 8 UVPROM, 200 ns, CDIP32 |
| 封裝： | CERDIP-32 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大小： | 50K |
| 代理商： | WS27C010L-20DMB |
SYMBOL
PARAMETER
CONDITIONS
TYP(6)
MAX
UNITS
CIN
Input Capacitance
VIN = 0V
4
6
pF
COUT
Output Capacitance
VOUT = 0V
8
12
pF
CVPP
VPP Capacitance
VPP = 0 V
18
25
pF
4-27
WS27C010L
AC READ TIMING DIAGRAM
tACC
tOH
ADDRESS VALID
VALID OUTPUT
ADDRESSES
VIH
VIL
tOE
tDF
tCE
CE
OE
VIH
VIL
VIH
VIL
HIGH Z
(5)
(4)
OUTPUT
CAPACITANCE(5) T
A = 25 °C, f = 1 MHz
100 pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
820
2.01 V
D.U.T.
A.C. TESTING INPUT/OUTPUT WAVEFORM
TEST LOAD (High Impedance Test Systems)
2.4
0.4
2.0
0.8
2.0
0.8
TEST
POINTS
NOTE: 7. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters.
A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between VCC and ground is recommended.
Inadequate decoupling may result in access time degradation or other transient performance failures.
NOTES: 5. This parameter is only sampled and is not 100% tested.
6. Typical values are for TA = 25°C and nominal supply voltages.
A.C. testing inputs are driven at 2.4 V for a logic "1" and 0.4 V
for a logic "0." Timing measurements are made at 2.0 V for a
logic "1" and 0.8 V for a logic "0".
NOTE:
4. OE may be delayed up to tCE – tOE after the falling edge of CE without impact on tCE.
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