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參數(shù)資料
| 型號： | WME128K8-125CMA |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 128K X 8 EEPROM 5V, 125 ns, CDIP32 |
| 封裝： | 0.600 INCH, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 320K |
| 代理商： | WME128K8-125CMA |
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WME128K8-XXX
January 2008
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
READ
Figure 3 shows Read cycle waveforms. A read cycle begins
with selection address, chip select and output enable. Chip
select is accomplished by placing the CS# line low. Output
enable is done by placing the OE# line low. The memory
places the selected data byte on I/O0 through I/O7 after
the access time. The output of the memory is placed in a
high impedance state shortly after either the OE# line or
CS# line is returned to a high level.
FIGURE 3 – READ WAVEFORMS
t
ADDRESS
CS#
OE#
OUTPUT
OH
tDF
tACC
t RC
t OE
tACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
NOTE:
OE# may be delayed up to tACS- tOE after the falling edge of CS#
without impact on tOE or by tACC- tOE after an address change without impact on tACC.
AC READ CHARACTERISTICS
(See Figure 3)
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Read Cycle Parameter
Symbol
-125
-140
-150
-200
-250
-300
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
125
140
150
200
250
300
ns
Address Access Time
tACC
125
140
150
200
250
300
ns
Chip Select Access Time
tACS
125
140
150
200
250
300
ns
Output Hold from Address
Change, OE# or CS#
tOH
000000
ns
Output Enable to Output Valid
tOE
55
85
ns
Chip Select or OE# to High
Z Output
tDF
63
70
ns
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| WME128K8-140CC | 制造商:Microsemi Corporation 功能描述:128K X 8 EEPROM MONOLITHIC, 140NS, 32 DIP, COMMERCIAL SCREEN - Bulk |
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