參數(shù)資料
型號(hào): WEDPN4M64V-100BI
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類(lèi): DRAM
英文描述: 4M X 64 SYNCHRONOUS DRAM, 7 ns, PBGA219
封裝: 21 X 21 MM, PLASTIC, BGA-219
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 385K
代理商: WEDPN4M64V-100BI
10
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specications without notice.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter
Symbol
-100
-125
-133
Unit
Min
Max
Min
Max
Min
Max
Access time from CK (pos. edge)
CL = 3
tAC
7
6
5.5
ns
CL = 2
tAC
766
ns
Address hold time
tAH
1
0.8
ns
Address setup time
tAS
2
1.5
ns
CK high-level width
tCH
3
2.5
ns
CK low-level width
tCL
3
2.5
ns
Clock cycle time (22)
CL = 3
tCK
10
8
7.5
ns
CL = 2
tCK
13
10
CKE hold time
tCKH
1
0.8
ns
CKE setup time
tCKS
2
1.5
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
1
0.8
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
2
1.5
ns
Data-in hold time
tDH
1
0.8
ns
Data-in setup time
tDS
2
1.5
ns
Data-out high-impedance time
CL = 3 (10)
tHZ
7
6
5.5
ns
CL = 2 (10)
tHZ
7
6
ns
Data-out low-impedance time
tLZ
1
ns
Data-out hold time (load)
tOH
3
ns
Data-out hold time (no load) (26)
tOHN
1.8
ns
ACTIVE to PRECHARGE command
tRAS
50
120,000
50
120,000
50
120,000
ns
ACTIVE to ACTIVE command period
tRC
70
68
ns
ACTIVE to READ or WRITE delay
tRCD
20
ns
Refresh period (4,096 rows) – Commercial, Industrial
tREF
64
ms
Refresh period (4,096 rows) – Military
tREF
16
ms
AUTO REFRESH period
tRFC
70
ns
PRECHARGE command period
tRP
20
ns
ACTIVE bank A to ACTIVE bank B command
tRRD
20
ns
Transition time (7)
tT
0.3
1.2
0.3
1.2
0.3
1.2
ns
WRITE recovery time
(23)
tWR
1 CK + 7ns
1 CK + 7.5
(24)
15
ns
Exit SELF REFRESH to ACTIVE command
tXSR
80
75
ns
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