參數(shù)資料
型號(hào)： WED8L24258V15BI
元件分類： SRAM
英文描述： 256K X 24 STANDARD SRAM, 15 ns, PBGA119
封裝： BGA-119
文件頁(yè)數(shù)： 1/5頁(yè)
文件大?。?/td> 113K
代理商： WED8L24258V15BI
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED8L24258V
March 2000 Rev. 0
ECO #12475
FIG. 1
PIN NAMES
BLOCK DIAGRAM
PIN SYMBOLS
PIN CONFIGURATION
Asynchronous SRAM, 3.3V, 256Kx24
FEATURES
256Kx24 bit CMOS Static
Random Access Memory Array
Fast Access Times: 10, 12, and 15ns
Master Output Enable and Write Control
Three Chip Enables for Byte Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
119 Lead BGA (JEDEC MO-163), No. 391
Small Footprint, 14mmx22mm
Multiple Ground Pins for Maximum Noise Immunity
Single +3.3V (
±5%) Supply Operation
DSP Memory Solution
Motorola DSP5630x
Analog Devices SHARCTM
DESCRIPTION
The WED8L24258VxxBC is a 3.3V, twelve megabit SRAM con-
structed with three 256Kx8 die mounted on a multi-layer laminate
substrate. With 10 to 15ns access times, x24 width and a 3.3V
operating voltage, the WED8L24258V is ideal for creating a single chip
memory solution for the Motorola DSP5630x or a two chip solution
for the Analog Devices SHARCTM DSP.
The single or dual chip memory solutions offer improved system
performance by reducing the length of board traces and the number
of board connections compared to using multiple monolithic devices.
The JEDEC Standard 119 lead BGA provides a 69% space savings
over using six 256Kx4, 300 mil wide SOJs and the BGA package
has a maximum height of 110 mils compared to 148 mils for the SOJ
packages. The BGA package also allows the use of the same
manufacturing and inspection techniques as the Motorola DSP, which
is also in a BGA package.
12
3
4
5
6
7
AN C
AO
A1
A2
A3
A4
N C
B
N C
A5A6E0A7
A8
N C
C
I/012
NC
E2
NC
E3
NC
I/00
D
I/013
VCC
GND
VCC
I/01
E
I/014
GND
VCC
GND
VCC
GND
I/02
F
I/015
VCC
GND
VCC
I/03
G
I/016
GND
VCC
GND
VCC
GND
I/04
H
I/017
VCC
GND
VCC
I/05
J
N C
GND
VCC
GND
VCC
GND
N C
K
I/018
VCC
GND
VCC
I/06
L
I/019
GND
VCC
GND
VCC
GND
I/07
M
I/020
VCC
GND
VCC
I/08
N
I/021
GND
VCC
GND
VCC
GND
I/09
P
I/022
VCC
GND
VCC
I/010
R
I/023
NC
A17
I/011
T
N C
A9
A10W
A11
A12
N C
U
N C
A13
A14
G
A15
A16
N C
A0-17
Address Inputs
E
Chip Enable
W
Master Write Enable
G
Master Output Enable
DQ0-23
Common Data Input/Output
VCC
Power (3.3V
±5%)
GND
Ground
NC
No Connection
256K x 24
Memory
Array
18
A0-A17
G
W
E0
E2
E3
DQ0-7
DQ8-15
DQ16-23
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