- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄204017 > WED3DL328V12BC 8M X 32 SYNCHRONOUS DRAM MODULE, 8 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號： | WED3DL328V12BC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM MODULE, 8 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 409K |
| 代理商： | WED3DL328V12BC |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED3DL328V
October 2000 Rev. 0
ECO #13253
8Mx32 SDRAM
FEATURES
s 53% Space Savings vs. Monolithic Solution
s Reduced System Inductance and Capacitance
s Pinout and Footprint Compatible to SSRAM 119 BGA
s 3.3V Operating Supply Voltage
s Fully Synchronous to Positive Clock Edge
s Clock Frequencies of 125MHz and 83MHz
s Burst Operation
Sequential or Interleave
Burst Length = Programmable 1, 2, 4, 8 or Full Page
Burst Read and Write
Multiple Burst Read and Single Write
s Data Mask Control Per Byte
s Auto and Self Refresh
s Automatic and Controlled Precharge Commands
s Suspend Mode and Power Down Mode
s 119 Pin BGA, JEDEC MO-163
The WED3DL328V is an 8Mx32 Synchronous DRAM configured
as 4x2Mx32. The SDRAM BGA is constructed with two 8Mx16
SDRAM die mounted on a multi-layer laminate substrate and
packaged in a 119 lead, 14mm by 22mm, BGA.
The WED3DL328V is an ideal memory solution for the Texas
Instruments’ TMS320C6000 family of 32 bit DSPs providing a
direct interface to the combined memory ports of the TMS320C,
C6211 and C6711. The compatibility with the SSRAM 119BGA
footprint allows for a single systems design to utilize either
SSRAM or SDRAM.
The WED3DL328V is available in clock speeds of 125MHz,
100MHz and 83MHz. The range of operating frequencies, pro-
grammable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high
performance memory system applications.
The package and design provides performance enhancements
via a 50% reduction in capacitance vs. two monolithic devices.
The design includes internal ground and power planes which
reduces inductance on the ground and power pins allowing for
improved decoupling and a reduction in system noise.
FIG. 1
*NOTE:
Pin B3 is designated as NC/A12. This pin is used for future density upgrades as address pin A12.
PIN DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
PRELIMINARY
DESCRIPTION
A0 – A11
Address Bus
BA0-1
Bank Select Addresses
DQ
Data Bus
CLK
Clock
CKE
Clock Enable
DQM
Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
CE
Chip Enable
VDD
Power Supply pins, 3.3V
VDDQ
Data Bus Power Supply pins,3.3V
VSS
Ground pins
12
34
56
7
AVDDQ
NC
BA
0
NC
A
10
A
7
VDDQ
A
B
NC
NC/A12*
CAS
A11
NC
B
CNC
NC
BA 1
VDD
A9
A8
NC
C
D
DQC
NC
VSS
NC
VSS
NC
DQB
D
E
DQC
VSS
CE
VSS
DQB
E
F
VDDQ
DQC
VSS
RAS
VSS
DQB
VDDQ
F
G
DQC
DQMC
NC
DQMB
DQB
G
H
DQC
VSS
CKE
VSS
DQB
H
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
J
K
DQD
VSS
CLK
VSS
DQADQAK
L
DQD
DQMD
NC
DQMADQA DQA L
M
VDDQ
DQD
VSS
WE
VSS
DQAVDDQ
M
N
DQD
VSS
A
1
VSS
DQADQAN
P
DQD
NC
VSS
A0
VSS
NC
DQA
P
R
NC
A6NC
VDD
NC
A2NC
R
TNC
NC
A5
A4
A3
NC
T
U
VDDQ
NC
VDDQ
U
12
34
56
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WED3EG6416S265D4 | 16M X 64 DDR DRAM MODULE, DMA200 |
| WED3EG6416S202D4 | 16M X 64 DDR DRAM MODULE, DMA200 |
| WED3EG6416S265D4 | 16M X 64 DDR DRAM MODULE, DMA200 |
| WED3EG6416S262D4 | 16M X 64 DDR DRAM MODULE, DMA200 |
| WED3EG6418S202D4 | 16M X 64 DDR DRAM MODULE, DMA200 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED3DL328V7BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V8BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX32|CMOS|BGA|119PIN|PLASTIC |
| WED3DL328V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TMS320C6000 Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。