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參數(shù)資料
| 型號： | WED3DG7264V75D1 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, ZMA144 |
| 封裝： | SODIMM-144 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 249K |
| 代理商： | WED3DG7264V75D1 |
WED3DG7264V-D1
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
July 2005
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
VCC = 3.3V ±0.3V, 0°C ≤ TA ≤ +70°C
AC CHARACTERISTICS
7
75/10
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from CLK (pos. edge)
CL = 3
tAC(3)
5.4
ns
27
CL = 2
tAC(2)
5.4
6
ns
Address hold time
tAH
0.8
ns
Address setup time
tAS
1.5
ns
CLK high-level width
tCH
2.5
ns
CLK low-level width
tCL
2.5
ns
Clock cycle time
CL = 3
tCK(3)
7
7.5
ns
23
CL = 2
tCK(2)
7.5
10
ns
23
CKE hold time
tCKH
0.8
ns
CKE setup time
tCKS
1.5
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
0.8
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
ns
Data-in hold time
tDH
0.8
ns
Data-in setup time
tDS
1.5
ns
Data-out high-impedance time
CL = 3
tHZ(3)
5.4
ns
10
CL = 2
tHZ(2)
5.4
6
ns
10
Data-out low-impedance time
tLZ
11
ns
Data-out hold time (load)
tOH
2.7
ns
Data-out hold time (no load)
tOHN
1.8
ns
28
ACTIVE to PRECHARGE command
tRAS
37
120K
44
120K
ns
ACTIVE to ACTIVE command period
tRC
60
66
ns
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
Refresh period (8,192 rows)
tREF
64
ms
AUTO REFRESH period
tRFC
66
ns
PRECHARGE command period
tRP
15
20
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
14
15
ns
Transition time
tT
0.3
1.2
0.3
1.2
ns
7
WRITE recovery time
tWR
1 CLK +
7ns
1 CLK +
7ns
-24
14
15
ns
14, 25
Exit SELF REFRESH to ACTIVE command
tXSR
67
75
ns
20
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