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參數(shù)資料
| 型號(hào)： | WED3DG644V7D1I-SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 4M X 64 SYNCHRONOUS DRAM MODULE, ZMA144 |
| 封裝： | ROHS COMPLIANT, SODIMM-144 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | WED3DG644V7D1I-SG |
WED3DG644V-D1
White Electronic Designs
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
September 2007
Rev. 5
OPERATING CURRENT CHARACTERISTICS
(VCC = 3.3V, TA = 0°C to +70°C)
Parameter
Symbol
Conditions
Version
Units
Note
133/100
Operating Current
(One bank active)
ICC1
Burst Length = 1
tRC tRC(min)
IOL = 0mA
300
mA
1
Precharge Standby Current
in Power Down Mode
ICC2P
CKE VIL(max), tCC = 10ns
4
mA
ICC2PS
CKE & CLK VIL(max), tCC = ∞
4
Precharge Standby Current
in Non-Power Down Mode
ICC2N
CKE VIH(min), CS VIH(min), tcc =10ns
Input signals are charged one time during 20
48
mA
ICC2NS
CKE VIH(min), CLK VIL(max), tCC = ∞
Input signals are stable
24
Active Standby Current in
Power-Down Mode
ICC3P
CKE VIL(max), tCC = 10ns
8
mA
ICC3PS
CKE & CLK VIL(max), tCC = ∞
8
Active Standby Current in
Non-Power Down Mode
ICC3N
CKE VIH(min), CS VIH(min), tcc = 10ns
Input signals are changed one time during 20ns
80
mA
ICC3NS
CKE VIH(min), CLK VIL(max), tcc = ∞
Input signals are stable
40
mA
Operating Current (Burst mode)
ICC4
Io = mA
Page burst
4 Banks activated
tCCD = 2CLK
460
mA
1
Refresh Current
ICC5
tRC tRC(min)
360
mA
2
Self Refresh Current
ICC6
CKE 0.2V
4mA
Notes:
1.
Measured with outputs open.
2.
Refresh period is 64ms.
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相關(guān)代理商/技術(shù)參數(shù) |
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| WED3DG644V-D1 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SDRAM Modules - 144 Pin SO-DIMM. Unbuffered |
| WED3DG644V-D2 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SDRAM Modules - 168 Pin DIMM. Unbuffered |
| WED3DG6463V-D2 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SDRAM Modules - 168 Pin DIMM. Unbuffered |
| WED3DG6464V-D1 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SDRAM Modules - 144 Pin SO-DIMM. Unbuffered. w/PLL |
| WED3DG6464V-D2 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SDRAM Modules - 168 Pin DIMM. Unbuffered |
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