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參數(shù)資料
| 型號： | WED3DG644V75D1I-MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 64 SYNCHRONOUS DRAM MODULE, ZMA144 |
| 封裝： | ROHS COMPLIANT, SODIMM-144 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 199K |
| 代理商： | WED3DG644V75D1I-MG |
WED3DG644V-D1
White Electronic Designs
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
September 2007
Rev. 5
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
-1.0 ~ 4.6
V
Storage Temperature
TSTG
-55 ~ +150
°C
Power Dissipation
PD
4
W
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
VCC
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0
VCCQ+0.3
V1
Input Low Voltage
VIL
-0.3
—
0.8
V
2
Output High Voltage
VOH
2.4
—
V
IOH= -2mA
Output Low Voltage
VOL
——
0.4
V
IOL= -2mA
Input Leakage Current
ILI
-10
—
10
μA3
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VCCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-State outputs.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V ± 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
CIN1
25
pF
Input Capacitance (RAS#,CAS#,WE#)
CIN2
25
pF
Input Capacitance (CKE0)
CIN3
25
pF
Input Capacitance (CLK0)
CIN4
19
pF
Input Capacitance (CS0#)
CIN5
25
pF
Input Capacitance (DQM0-DQM7)
CIN6
8pF
Input Capacitance (BA0-BA1)
CIN7
25
pF
Data Input/Output Capacitance (DQ0-DQ63)
COUT
10
pF
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C
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