參數(shù)資料
型號(hào)： WED2ZL236512S38BC
英文描述： Synchronous Pipeline Burst NBL SRAM(2 x 512K x 36,3.8ns同步脈沖流水線(xiàn)靜態(tài)RAM(無(wú)總線(xiàn)等待時(shí)間）)
中文描述： 管道爆裂NBL的同步SRAM的（2 ×為512k × 36,3.8納秒同步脈沖流水線(xiàn)靜態(tài)隨機(jī)存儲(chǔ)器（無(wú)總線(xiàn)等待時(shí)間））
文件頁(yè)數(shù)： 1/12頁(yè)
文件大?。?/td> 213K
代理商： WED2ZL236512S38BC
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2ZL236512S
October 2000 Rev. 2
ECO #13239
DESCRIPTION
The WEDC SyncBurst - SRAM famly employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 32Mb SyncBurst SRAMs integrate two 512K x 36
SRAMs into a single BGA package to provide 2 x 512K x 36
configuration. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single-clock input (CLK). The
NBL or No Bus Latency Memory utilizes all the bandwidth in any
combination of operating cycles. Address, data inputs, and all
control signals except output enable and linear burst order are
synchronized to input clock. Burst order control must be tied “High
or Low.” Asynchronous inputs include the sleep mode enable (ZZ).
Output Enable controls the outputs at any given time. Write cycles
are internally self-timed and initiated by the rising edge of the clock
input. This feature elimnates complex off-chip write pulse genera-
tion and provides increased timng flexibility for incomng signals.
* Ths datasheet describes aproduct under deveopment, not fuly
characterized andis subect to changewthout notice
2 x 512K x 36 Synchronous Pipeline Burst NBL SRAM
PRELIMINARY*
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
CLK
CKE
SA
ADV
OE
WE
BWa
BWb
BWc
BWd
LBO
ZZ
CEa
512K x 36
SSRAM
DQ
a
-
DQ
d
DQPa
-
DQP
d
512K x 36
SSRAM
CEb
FEATURES
I
Fast clock speed: 166, 150, 133, and 100MHz
I
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
I
Fast OE access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
I
Single +2.5V
±
5% power supply (V
DD
)
I
Snooze Mode for reduced-standby power
I
Individual Byte Write control
I
Clock-controlled and registered addresses, data I/Os and
control signals
I
Burst control (interleaved or linear burst)
I
Packaging:
119-bump BGA package
I
Low capacitive bus loading
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DD
SA
NC
DQ
c
DQ
c
V
DD
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
V
DD
DQ
d
DQ
d
DNC
DNC
V
DD
SA
CEa
SA
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
SA
NC
NC
SA
SA
SA
V
SS
V
SS
V
SS
BW
c
V
SS
DNC
V
SS
BW
d
V
SS
V
SS
V
SS
LBO
SA
NC
SA
ADV
V
DD
DNC
DNC
OE
DNC
WE
V
DD
CLK
NC
CKE
SA1
SA0
V
DD
SA
NC
SA
SA
SA
V
SS
V
SS
V
SS
BW
b
V
SS
DNC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
SA
NC
SA
CEb
SA
DQP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
SA
NC
NC
V
DD
DNC
DNC
DQ
b
DQ
b
V
DD
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
V
DD
DQ
a
DQ
a
NC
ZZ
V
DD
Note:
DNC = Do Not Connect. Connections to these pins
may cause the device to not function properly.
相關(guān)PDF資料
PDF描述
WED2ZL236512S42BC Synchronous Pipeline Burst NBL SRAM(2 x 512K x 36,4.2ns同步脈沖流水線(xiàn)靜態(tài)RAM(無(wú)總線(xiàn)等待時(shí)間）)
WED2ZL361MS50BC 1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,5.0ns同步脈沖流水線(xiàn)靜態(tài)RAM(無(wú)總線(xiàn)等待時(shí)間）)
WED2ZL361MS35BC 1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,3.5ns同步脈沖流水線(xiàn)靜態(tài)RAM(無(wú)總線(xiàn)等待時(shí)間）)
WED2ZL361MS38BC 1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,3.8ns同步脈沖流水線(xiàn)靜態(tài)RAM(無(wú)總線(xiàn)等待時(shí)間）)
WED2ZL361MS42BC 1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,4.2ns同步脈沖流水線(xiàn)靜態(tài)RAM(無(wú)總線(xiàn)等待時(shí)間）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
WED2ZL236512S-BC 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:NBL SSRAM MCP
WED2ZL361MS 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM
WED2ZL361MS26BC 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM
WED2ZL361MS26BI 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM
WED2ZL361MS28BC 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM
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