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參數(shù)資料
| 型號(hào)： | WED2DL36514AV38BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 3.8 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | WED2DL36514AV38BC |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL36513V
WED2DL36513AV
FIG. 3 READ TIMING DIAGRAM
ADSP
ADSC
ADDRESS
BWx, GW
CE
(NOTE 2)
tADSS
tADSH
ADV
OE
CLOCK
A2
A1
tAS
tAH
Q
tAAS
tAAH
Q(A2)Q(A2+1)
tKH
tKL
tKC
tKQ
Q(A2+3)
Q(A2+1)
Q(A1)
Q(A2+2)
tKQLZ
tOELZ
tKQ
tOEQ
tOEHZ
SINGLE READ
BURST READ
Q(A2)
tKQHZ
(NOTE 3)
A3
DON’T CARE
UNDEFINED
Deselect Cycle
(NOTE 4)
ADV suspends burst
tCSS tCSH
tWS
tWA
Burst continued with
new base address
Burst wraps around
to its initial state
(NOTE 1)
HIGH-Z
tKQX
NOTES:
1. Q (A2) refers to output from address A2. Q (A2+1) refers to output from the next internal burst address following A2.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and
CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the
following clock rising edge.
4. Outputs are disabled within one clock cycle after deselect.
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