參數(shù)資料
型號(hào)： WD512K32NV-20H1IA
英文描述： 512Kx32 SRAM 3.3V MULTICHIP PACKAGE
中文描述： 512Kx32 SRAM的3.3多芯片封裝
文件頁(yè)數(shù)： 1/7頁(yè)
文件大小： 302K
代理商： WD512K32NV-20H1IA
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WS512K32V-XXX
March 2006
Rev. 12
512Kx32 SRAM 3.3V MULTICHIP PACKAGE
FEATURES
Access Times of 15, 17, 20ns
Low Voltage Operation
Packaging
66-pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400)
68 lead, 22.4mm (0.880 inch) CQFP, (G2U),
3.56mm (0.140"), (Package 510)
Organized as 512Kx32; User Configurable as
2x512Kx16 or 4x512Kx8
Commercial, Industrial and Military Temperature
Ranges
Low Voltage Operation:
3.3V ± 10% Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
Fully Static Operation:
No clock or refresh required.
Three State Output.
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight
WS512K32V-XG2UX - 8 grams typical
WS512K32NV-XH1X - 13 grams typical
* This product is subject to change without notice.
PIN CONFIGURATION FOR WS512K32NV-XH1X
Pin Description
I/O
0-31
Data Inputs/Outputs
A
0-18
Address Inputs
WE
1-4
#
Write Enables
CS
1-4
#
Chip Selects
OE#
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
Top View
Block Diagram
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
18
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
#
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
WE
1
# CS
1
#
CS
2
#
CS
3
#
CS
4
#
WE
4
#
WE
3
#
WE
2
#
512K x 8
512K x 8
512K x 8
512K x 8
OE#
A
0-18
I/O
0-7
I/O
24-31
I/O
16-23
I/O
8-15
8
8
8
8
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