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參數資料
| 型號： | WB1330X |
| 英文描述： | Serial-Input Frequency Synthesizer |
| 中文描述： | 串行輸入頻率合成器 |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 160K |
| 代理商： | WB1330X |
Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers
WB1330
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 11, 2000, rev. *B
Features
Operating voltage 2.7V to 5.5V
PLL1 operating frequency:
— 2.5 GHz with prescaler ratios of 32/33 and 64/65
PLL2 operating frequency:
— 600 MHz with prescaler ratios of 8/9 and 16/17
Lock detect feature
Power-down mode ICC < 1 A typical at 3.0V
20-pin TSSOP (Thin Shrink Small Outline Package)
Applications
The Cypress WB1330 is a dual serial input PLL frequency
synthesizer designed to combine the RF and IF mixer frequen-
cy sections of wireless communications systems. One 2.5-
GHz and one 600-MHz prescaler, each with pulse swallow ca-
pability are included. The device operates from 2.7V and dis-
sipates only 30 mW. (See Figure 1 for an example application
diagram of the WB1330.)
WB1330 Dual Hi-Lo PLL Block Diagram
Pin Configuration
VCC2
VP2
DOPLL2
GND
FIN2
FIN2#
GND
LE
DATA
CLOCK
20
19
18
17
16
15
14
13
12
11
VCC1
VP1
DOPLL1
GND
FIN1
FIN1#
GND
OSC_IN
GND
FO/LD
1
2
3
4
5
6
7
8
9
10
Binary 7-Bit
Prescaler
Phase
Detector
19-Bit
Pwr-dwn
Swallow Counter
Binary 11-Bit
Programmable Counter
32/33 or
Latch
PLL1
20-Bit Latch
Prescaler
8/9 or
Cntrl 22-Bit
Shift
Reg.
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
19-Bit
Pwr-dwn
Latch
PLL2
15-Bit
Reference Counter
15-Bit
Reference Counter
Phase
Detector
Charge
Pump
fr fp
Monitor
Output
Charge
Pump
Power
Control
Selector
GND (17)
VP2 (19)
GND (9)
GND (14)
GND (4)
GND (7)
VCC1 (1)
VCC2 (20)
FIN1 (5)
FIN1# (6)
OSC_IN (8)
LE (13)
DATA (12)
CLOCK (11)
FIN2 (16)
FIN2# (15)
VP1 (2)
DOPLL1 (3)
FO/LD (10)
DOPLL2 (18)
Latch
Selector
fp1
fr1
fr2
fp2
64/65
16/17
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