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參數(shù)資料
| 型號(hào)： | W9812G21H-6I |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, TSOP2-86 |
| 文件頁數(shù)： | 32/36頁 |
| 文件大小： | 1422K |
| 代理商： | W9812G21H-6I |
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W9812G2IH
Publication Release Date:Nov. 06, 2008
- 5 -
Revision A01
5
PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
25-27, 60-66, 24,21
A0
A11
Address
Multiplexed pins for row and column address. Row
address: A0
A11. Column address: A0A7. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
22,23
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
2,4,5,7,8,10,11,13,74,
76,77,79,80,82,83,85,
31,33,34,36,37,39,40,
42,45,47,48,50,51,53,
54,56
DQ0
DQ31
Data Input/
Output
Multiplexed pins for data output and input.
20
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and
previous operation continues.
19
RAS
Row
Address
Strobe
Command input. When sampled at the rising edge of the
clock,
RAS , CAS and WE define the operation to be
executed.
18
CAS
Column
Address Strobe Referred to RAS
17
WE
Write Enable
Referred to
RAS
16,71,28,59
DQM0~3
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with zero
latency.
68
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
67
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
1,15,29,43
VDD
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
44,58,72,86
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
3,9,35,41,49,55,75,81
VDDQ
Power (+3.3V)
for I/O buffer
Separated power from VDD, to improve DQ noise
immunity.
6,12,32,38,46,52,78,
84
VSSQ
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise
immunity.
14,30,57,69,70,73
NC
No Connection No connection
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PDF描述 |
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| W9812G21H-6C | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9812G2GB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-6I | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GB-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 4 BANKS 】 32BITS SDRAM |
| W9812G2GH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:a high-speed synchronous dynamic random access memory (SDRAM), organized as 1,048,576 words 】 4 banks 】 32 bits |
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