參數(shù)資料
型號(hào): W78E858A40FL
廠商: Nuvoton Technology Corporation of America
文件頁(yè)數(shù): 31/35頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8-BIT 32K FLASH 44-PQFP
標(biāo)準(zhǔn)包裝: 96
系列: W78
核心處理器: 8052
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,串行端口
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-BQFP
包裝: 托盤
W78E858
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EA
I
External Access Enable: EA low forces the processor to execute the
external ROM. The ROM address and data will not be present on the bus if
the EA pin is high and the program counter is within the 32 KB area.
Otherwise they will be present on the bus.
PSEN
O/H
Program Strobe Enable: PSEN enables the external ROM data in the Port 0
address/data bus. When internal ROM access is performed, no PSEN strobe
signal outputs originate from this pin.
ALE
O/H
Address Latch Enable: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency. An ALE pulse is omitted during external data memory
accesses.
RST
I/L
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device. RST has a Schmitt trigger input stage to provide
additional noise immunity with a slow rising input voltage.
XTAL1
I
Crystal 1: This is the crystal oscillator input. This pin may be driven by an
external clock
XTAL2
O
Crystal 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS
I
Ground: Ground potential.
VDD
I
Power Supply: Supply voltage for operation.
P0.0
P0.7
I/O D
Port 0: Function is the same as that of the standard 8052.
P1.0
P1.7
I/O H
Port 1: Function is the same as that of the standard 8052. Port1 also service
the alternative function INT2
INT9. P1.0 provide a timer2 programmable
clock output. Four channel PWM clock output via P1.4
P1.7
P2.0
P2.7
I/O H
Port 2: Port 2 is a bi-directional I/O port with internal pull-ups and emits the
high-order address byte during accesses external memory
P3.0
P3.7
I/O H
Port 3: Function is the same as that of the standard 8052
P4.0
P4.3
I/O H
Port 4: Function is the same as Port1
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Publication Release Date: April 22, 2008
- 5 -
Revision A8
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