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參數(shù)資料
| 型號： | W42C27 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Specialty Clock Generator(專用時(shí)鐘發(fā)生器) |
| 中文描述： | 專業(yè)時(shí)鐘發(fā)生器（專用時(shí)鐘發(fā)生器） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 100K |
| 代理商： | W42C27 |
Specialty Clock Generator
W42C27
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
September 28, 1999, rev. **
408-943-2600
Features
Supports 3.3V and 5V operation
W42C27-36 provides the same functionality but stron-
ger output drive than the W42C27-13 (obsolete)
Proprietary crystal oscillator circuitry provides low REF
jitter, excellent duty cycle
Integral PLL loop filter components ensure stable PLL
operation in noisy system environments
Output clocks are TTL or CMOS-level compatible
Custom options available with metal layer changes
Low power CMOS design available in:
—8-pin SOIC (Small Outline Integrated Circuit)
Table 1. Input/Output Frequency Selection
W42C27-41
FS1
FS0
Reference
(input)
CLK
Ratio (P/Q)
0
0
17.734
48.625
85/31
0
1
17.734
96.059
65/12
1
0
14.318
48.682
17/5
1
1
14.318
96.016
114/17
Table 2. Product Selection Guide
Part
Input
(MHz)
Output
(MHz)
Application
-36
17
106.25
Fibre Channel
-41
14.318
Selectable
Digital Cameras
Pin Configurations
Functional Block Diagram: W42C27 Base Feature Set
AGND
GND
X1
X2
1
2
3
4
8
7
6
5
106.25MHz
AV
DD
V
DD
OE
W42C27-36
FS0
GND
X1
X2
1
2
3
4
8
7
6
5
FS1
REF
V
DD
CLK
W42C27-41
STOPCPU
SLOWCPU
FS0
FS1
FS2
FS3
Frequency
Selection
ROM
÷P
–
PFD
+
VCO
Latched
Gate
÷d
÷2
OUT A
OUT B
OUT C
OE
M
Loop
Filter
÷Q
Crystal
Oscillator
÷2
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