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參數(shù)資料
| 型號(hào)： | W3HG264M72EER806AD7M |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, DMA244 |
| 封裝： | MINIDIMM-244 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 211K |
| 代理商： | W3HG264M72EER806AD7M |
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W3HG264M72EER-AD7
December 2005
Rev. 0
ADVANCED
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
26.
ODT turn-off time tAOF (MIN) is when the device starts to turn off
ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in
high impedance. Both are measured from tAOFD.
27.
This parameter has a two clock minimum requirement at any tCK.
28.
tDELAY is calculated from tIS + tCK + tIH so that CKE registration
LOW is guaranteed prior to CK, CK# being removed in a system
RESET condition.
29.
tISXR is equal to tIS and is used for CKE setup time during self
refresh exit.
30.
No more than 4 bank ACTIVE commands may be issued in
a given tFAW (MIN) period. tRRRD (MIN) restriction still applies.
The tFAW (MIN) parameter applies to all 8 bank DDR2 devices,
regardless of the number of banks already open or closed.
31.
tRPA timing applies when the PRECHARGE(ALL) command is
issued, regardless of the number of banks already open or closed.
If a single-bank PRECHARGE command is issued, tRP timing
applies. tRPA (MIN) applies to all 8-bank DDR2 devices.
32.
Value is minimum pulse width, not the number of clock
registrations.
33.
Applicable to Read cycles only. Write cycles generally require
additional time due to Write recovery time (tWR) during arto
precharge.
34.
tCKE (MIN) of 3 clocks means CKE must be registered on three
consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the 3 clocks of
registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + 2* tCK + tIH.
35.
This parameter is not referenced to a specic voltage level, but
specied when the device output is no longer driving (tRPST) or
beginning to drive (tRPRE).
36.
When DQS is used single-ended, the minimum limit is reduced by
100ps.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG264M72EER806AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER-AD7 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EERXXXAD7MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EERXXXAD7SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG64M72EER403AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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