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參數(shù)資料
| 型號： | W3HG256M72AER403AD6MG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, RDIMM-240 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 256K |
| 代理商： | W3HG256M72AER403AD6MG |
W3HG256M72AER-AD6
11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2007
Rev. 1
23.
ODT turn-on time tAON (MIN) is when the device leaves High-Z and
ODT resistance begins to turn on. ODT turn-on time tAON (MAX)
is when the ODT resistance is fully on. Both are measured from
tAOND.
24.
ODT turn-off time tAOF (MIN) is when the device starts to turn off
ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in
High-Z. Both are measured from tAOFD.
25.
This parameter has a two clock minimum requirement at any tCK.
26.
tDELAY is calculated from tIS + tCK + tIH so that CKE registration
LOW is guaranteed prior to CK, CK# being removed in a system
RESET condition.
27.
tISXR is equal to tIS and is used for CKE setup time during self
refresh exit.
28.
No more than four bank-ACTIVE commands may be issued in a
given tFAW (MIN) period. tRRD (MIN) restriction still applies. The tFAW
(MIN) parameter applies to all 8-bank DDR2 devices, regardless of
the number of banks already open or closed.
29.
tRPA timing applies when the PRECHARGE (ALL) command is
issued, regardless of the number of banks already open or closed.
If a single-bank PRECHARGE command is issued, tRP timing
applies. tRPA (MIN) applies to all 8-bank DDR2 devices.
30.
N/A
31.
This is applicable to READ cycles only. WRITE cycles generally
require additional time due to tWR during auto precharge.
32.
tCKE (MIN) of three clocks means CKE must be registered on three
consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the three clocks of
registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + 2 x tCK + tIH.
33.
This parameter is not referenced to a specic voltage level, but
specied when the device output is no longer driving (tRPST) or
beginning to drive (tRPRE).
34.
1. When DQS is used single-ended, the minimum limit is reduced
by 100ps.
35.
1. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty
cycle. This half-clock value must be derated by the amount of
half-clock duty cycle error. For example, if the clock duty cycle was
47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN)
and 2.5 + 0.03, or 2.53, for tAOF (MAX).
36.
The clock’s tCKAVG is the average clock over any 200 consecutive
clocks and tCKAVG (MIN) is the smallest clock rate allowed, except
a deviation due to allowed clock jitter. Input clock jitter is allowed
provided it does not exceed values specied. Also, the jitter must
be of a random Gaussian distribution in nature.
37.
The inputs to the DRAM must be aligned to the associated clock;
that is, the actual clock that latches it in. However, the input timing
(in ns) references to the tCKAVG when determining the required
number of clocks. The following input parameters are determined
by taking the specied percentage times the tCKAVG rather than tCK:
tIPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.
38.
Spread spectrum is not included in the jitter specication values.
However, the input clock can accommodate spread spectrum at
a sweep rate in the range 20–60 KHz with additional one percent
of tCKAVG as a long-term jitter component; however, the spread
spectrum may not use a clock rate below tCKAVG(MIN) or above
tCKAVG(MAX).
39.
The period jitter (tJITPER) is the maximum deviation in the clock
period from the aver-age or nominal clock allowed in either
the positive or negative direction. JEDEC species tighter jitter
numbers during DLL locking time. During DLL lock time, the jitter
values should be 20 percent less than noted in the table (DLL
locked).
40.
The half-period jitter (tJITDTY) applies to either the high pulse of
clock or the low pulse of clock; however, the two cumulatively can
not exceed tJITPER.
41.
The cycle-to-cycle jitter (tJITCC) is the amount the clock period can
deviate from one cycle to the following cycle. JEDEC species
tighter jitter numbers during DLL locking time. During DLL lock
time, the jitter values should be 20 percent less than noted in the
table (DLL locked).
42.
The cumulative jitter error (tERRnPER), where n is 2, 3, 4, 5, 6–10,
or 11–50, is the amount of clock time allowed to consecutively
accumulate away from the average clock over any number of clock
cycles.
43.
The DRAM output timing is aligned to the nominal or average
clock. Most output parameters must be derated by the actual
jitter error when input clock jitter is present; this will result in
each parameter becoming larger. The following parameters are
required to be derated by subtracting tERR5PER (MAX): tAC (MIN),
tDQSCK (MIN), tLZDQS (MIN), tLZDQ (MIN), tAON (MIN); while these
following parameters are required to be derated by subtracting
tERR5PER (MIN): tAC (MAX), tDQSCK (MAX), tHZ (MAX), tLZDQS (MAX),
tLZDQ (MAX), tAON (MAX). The parameter tRPRE (MIN) is derated
by subtracting tJITPER (MAX), while tRPRE (MAX), is derated by
subtracting tJITPER (MIN). The parameter tRPST (MIN) is derated
by subtracting tJITDTY (MAX), while tRPST (MAX), is derated by
subtracting tJITDTY (MIN).
44.
Half-clock output parameters must be derated by the actual
tERR5PER and tJITDTY when input clock jitter is present; this will result
in each parameter becoming larger. The parameter tAOF (MIN) is
required to be derated by subtracting both tERR5PER (MAX) and
tJITDTY (MAX). The parameter tAOF (MAX) is required to be derated
by subtracting both tERR5PER (MIN) and tJITDTY (MIN).
45.
MIN(tCL, tCH) refers to the smaller of the actual clock LOW time
and the actual clock HIGH time driven to the device. The clock’s
half period must also be of a Gaussian distribution; tCHAVG and
tCLAVG must be met with or without clock jitter and with or without
duty cycle jitter. tCHAVG and tCLAVG are the average of any 200
consecutive CK falling edges.
46.
tHP (MIN) is the lesser of tCL and tCH actually applied to the device
CK and CK# inputs; thus, tHP (MIN) the lesser of tCLABS (MIN)
and tCHABS (MIN).
47.
1. tQH = tHP - tQHS; the worst case tQH would be the smaller of tCLABS
(MAX) or tCHABS (MAX) times tCKABS (MIN) - tQHS. Minimizing the
amount of tCHAVG offset and value of tJITDTY will provide a larger tQH,
which in turn will provide a larger valid data out window.
48.
1. JEDEC species using tERR6–10PER when derating clock-
related output timing (notes 43–44). Micron requires less derating
by allowing tERR5PER to be used.
49.
Requires 8 tCK for backward compatibility.
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| W3HG264M72EER403AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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| W3HG264M72EER-AD7 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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