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參數(shù)資料
| 型號： | W3HG256M72AER403AD6MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, RDIMM-240 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 256K |
| 代理商： | W3HG256M72AER403AD6MG |
W3HG256M72AER-AD6
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2007
Rev. 1
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION
AC CHARACTERISTICS
SYMBOL
806
667
534
403
UNIT
Notes
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock cycle time
CL = 6
tCK (6)
TBD
ps
CL = 5
tCK (5)
TBD
3,000
8,000
ps
16,
22,
36,
38
CL = 4
tCK (4)
TBD
3,750
8,000
3,750
8,000
5,000
8,000
ps
CL = 3
tCK (3)
TBD
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
TBD
0.48
0.52
0.48
0.52
0.48
0.52
tCK
45
CK low-level width
tCL
TBD
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Half clock period
tHP
TBD
MIN
(tCH,tCL)
MIN
(tCH,tCL)
MIN
(tCH,tCL)
ps
46
Clock
(absolute)
Absolute tCK
tCKabs
TBD
tCKAVG
PIN) +
JITPER
(MIN)
tCKAVG
PIN) +
JITPER
(MAX)
tCKAVG
PIN) +
JITPER
(MIN)
tCKAVG
PIN) +
JITPER
(MAX)
tCKAVG
PIN) +
JITPER
(MIN)
tCKAVG
PIN) +
JITPER
(MAX)
ps
Absolute CK high-
level width
tCHabs
TBD
tCKAVG
(MIN) *
tCHAVG
(MIN) +
tJITDTY
tCKAVG
(MAX) *
tCHAVG
(MAX) +
tJITDTY
tCKAVG
(MIN) *
tCHAVG
(MIN) +
tJITDTY
tCKAVG
(MAX) *
tCHAVG
(MAX) +
tJITDTY
tCKAVG
(MIN) *
tCHAVG
(MIN) +
tJITDTY
tCKAVG
(MAX) *
tCHAVG
(MAX) +
tJITDTY
ps
Absolute CK low-level
width
tCLabs
TBD
tCKAVG
*t(MIN)
CLAVG
t(MIN) +
JITDTY
(MIN)
tCKAVG
*t(MAX)
CLAVG
t(MIN) +
JITDTY
(MIN)
tCKAVG
*t(MIN)
CLAVG
t(MIN) +
JITDTY
(MIN)
tCKAVG
*t(MAX)
CLAVG
t(MIN) +
JITDTY
(MIN)
tCKAVG
*t(MIN)
CLAVG
t(MIN) +
JITDTY
(MIN)
tCKAVG
*t(MAX)
CLAVG
t(MIN) +
JITDTY
(MIN)
ps
Clock
Jitter
Clock jitter – period
tJITPER
TBD
-125
125
-125
125
-125
125
ps
39
Clock jitter – half
period
tJITDUTY
TBD
-125
125
-125
125
-150
150
ps
40
Clock jitter – cycle to
cycle
tJITCC
TBD
250
ps
41
Cumulative jitter
error, 2 cycles
tERR2per
TBD
-175
175
-175
175
-175
175
ps
42
Cumulative jitter
error, 3 cycles
tERR3per
TBD
-225
225
-225
225
-225
225
ps
Cumulative jitter
error, 4 cycles
tERR4per
TBD
-250
250
-250
250
-250
250
ps
Cumulative jitter
error, 5 cycles
tERR5per
TBD
-250
250
-250
250
-250
250
ps
42, 48
Cumulative jitter
error, 6–10 cycles
tERR6-10per
TBD
-350
350
-350
350
-350
350
ps
Cumulative jitter
error, 11–50 cycles
tERR11-
50per
TBD
-450
450
-450
450
-450
450
ps
42
Data hold skew factor
tQHS
TBD
-
340
-
400
-
450
ps
NOTE:
AC specication is based on
MICRON components. Other DRAM manufactures specication may be different.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG264M72EER403AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER534AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER665AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER806AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER-AD7 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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