- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄245706 > W3H64M72E-SBM (WHITE ELECTRONIC DESIGNS CORP) 64M X 72 DDR DRAM, PBGA208 PDF資料下載
參數(shù)資料
| 型號(hào)： | W3H64M72E-SBM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM, PBGA208 |
| 封裝： | 17 X 23 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 999K |
| 代理商： | W3H64M72E-SBM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
W3H64M72E-XSBX
16
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2006
Rev. 2
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
Function
CKE
CS#
RAS#
CAS#
WE#
BA2
BA1
BA0
A12
A11
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
LOAD MODE
H
LLLL
BA
OP Code
2
REFRESH
H
L
H
XXXX
SELF-REFRESH Entry
H
L
H
XXXX
SELF-REFRESH Exit
LH
H
XXX
XXXX
7
L
HHH
Single bank precharge
HH
L
H
L
X
L
X
2
All banks PRECHARGE
HH
L
H
L
X
H
X
Bank activate
H
L
H
L
BA
Row Address
WRITE
HH
L
H
L
BA
Column
Address
L
Column
Address
2, 3
WRITE with auto precharge
HH
L
H
L
BA
Column
Address
H
Column
Address
2, 3
READ
H
LH
BA
Column
Address
L
Column
Address
2, 3
READ with auto precharge
H
LH
BA
Column
Address
H
Column
Address
2, 3
NO OPERATION
H
X
L
H
XXXX
Device DESELECT
H
X
H
XXXXXXX
POWER-DOWN entry
HL
H
XXX
XXXX
4
L
HHH
POWER-DOWN exit
LH
H
XXX
XXXX
4
L
HHH
Note: 1. All DDR2 SDRAM commands are dened by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a dened logic level).
7. Self refresh exit is asynchronous.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WF4M8-150OPC5 | 4M X 8 FLASH 5V PROM, 150 ns, CDSO56 |
| WS128K32V-20HS | 512K X 8 MULTI DEVICE SRAM MODULE, 20 ns, HIP66 |
| WS128K32V-25HC | 512K X 8 MULTI DEVICE SRAM MODULE, 25 ns, HIP66 |
| WMD4M4-100F2M | 4M X 4 FAST PAGE DRAM, 100 ns, CDSO24 |
| WMF256K8-70CC5 | 256K X 8 FLASH 5V PROM, 70 ns, CDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H64M72E-XSBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3HG128M64EEU403D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU534D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU665D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU806D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。