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參數(shù)資料
| 型號(hào)： | W3EG72255S202AJD3SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.8 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大小： | 305K |
| 代理商： | W3EG72255S202AJD3SG |
W3EG72255S-D3
-JD3
-AJD3
5
White Electronic Designs
November 2004
Rev. 2
PRELIMINARY
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Parameter
Symbol
Rank 1
Conditions
DDR333@CL=2.5
Max
DDR266:@CL=2, 2.5
Max
DDR200@CL=2
Max
Units
Rank 2
Standby
State
Operating Current
IDD0
One device bank; Active - Precharge; tRC
= tRC (MIN); tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
4140
mA
IDD3N
Operating Current
IDD1
One device bank; Active-Read-Precharge
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
lOUT = 0mA; Address and control inputs
changing once per clock cycle.
4680
mA
IDD3N
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
180
rnA
IDD2P
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
1620
mA
IDD2F
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
1260
mA
IDD3P
Active Standby Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle.
1800
mA
IDD3N
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK =
tCK (MIN); lOUT = 0mA.
4770
mA
IDD3N
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
4590
rnA
IDD3N
Auto Refresh Current
IDD5
tRC = tRC (MIN)
7020
mA
IDD3N
Self Refresh Current
IDD6
CKE 0.2V
180
mA
IDD6
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
9090
9000
mA
IDD3N
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