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參數(shù)資料
| 型號： | W3EG6462S202D3 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 254K |
| 代理商： | W3EG6462S202D3 |
White Electronic Designs
W3EG6462S-D3
-JD3
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
May 2005
Rev. 4
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR400@
CL=3
Max
DDR333@
CL=2.5-3-3
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
2200
1960
1800
mA
Operating Current
IDD1
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
2480
2320
2080
mA
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
64
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
960
800
720
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
640
480
400
mA
Active Standby
Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
1120
960
800
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; TCK= TCK (MIN); lOUT = 0mA.
2720
2360
2000
mA
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK=tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
2680
2360
2000
rnA
Auto Refresh Current
IDD5
tRC = tRC (MIN)
3200
3000
2680
mA
Self Refresh Current
IDD6
CKE 0.2V
64
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK (MIN); Address and control
inputs change only during Active Read
or Write commands.
4880
4240
3600
mA
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| W3EG6462S202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S262D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S262JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S263D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S263JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
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