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參數(shù)資料
| 型號(hào)： | W3EG64128S265JD3SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 294K |
| 代理商： | W3EG64128S265JD3SG |
White Electronic Designs
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
December 2006
Rev. 6
W3EG64128S-D3
-JD3
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 299: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
335
262/263/265
202
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
PRECHARGE command period
tRP
15
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
10
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0000
ns
10,11
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
9
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
2111
tCK
Data valid output window
NA
tQH-tDQSQ
ns
13
REFRESH to REFRESH command interval
tREFC
70.3
μs12
Average periodic refresh interval
tREFI
7.8
μs12
Terminating voltage delay to VCC
tVTD
0000
ns
Exit SELF REFRESH to non-READ command
tXSNR
70
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
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| W3EG64128S335AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
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