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參數(shù)資料
| 型號： | W3EG2128M72AFSR-D3 |
| 英文描述： | 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA |
| 中文描述： | 2GB的- 2x128Mx72 ECC的DDR SDRAM的注冊，瓦特/鎖相環(huán)，F(xiàn)BGA封裝 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 285K |
| 代理商： | W3EG2128M72AFSR-D3 |
1
White Electronic Designs
January 2006
Rev. 3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
W3EG2128M72AFSR-D3
-AD3
FINAL*
FEATURES
Double-data-rate architecture
DDR266, DDR333, and DDR400
Bi-directional data strobes (DQS)
Phase-lock loop (PLL) clock driver to reduce
loading
Differential clock inputs (CK & CK#)
ECC error detection and correction
Programmable Read Latency 2, 2.5 (clock)
Programmable Burst Length (2, 4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
RoHS compliant products
Power Supply:
V
CC
= V
CCQ
= +2.5V ± 0.2 (133 and 166MHz)
V
CC
= V
CCQ
= +2.6V ± 0.1 (200MHz)
JEDEC standard 184 pin DIMM package
Package height options:
Low-profile: 30.48mm (1.20") MAX
NOTE: Consult factory for availability of:
Vendor source control options
Industrial temperature option
DESCRIPTION
The W3EG2128M72AFSR is a 2x128Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM components. The module consists of thirtysix
128Mx4 components, in FBGA packages mounted on a
184 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is subject to change without notice.
2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
2.5-3-3
DDR400@CL=3
200MHz
3-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2
133MHz
2-3-3
DDR266@CL=2.5
133MHz
2.5-3-3
Clock Speed
CL-t
RCD
-t
RP
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