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參數(shù)資料
| 型號： | W2Z1M72SJ35BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 1M X 72 MULTI DEVICE SRAM MODULE, 3.5 ns, PBGA209 |
| 封裝： | PLASTIC, BGA-209 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 624K |
| 代理商： | W2Z1M72SJ35BC |
2
White Electronic Designs Corporation Westborough, MA (508) 366-
5151
W2Z1M72SJ
BURST SEQUENCE TABLE
NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.
(Interleaved Burst, LBO = High)
Case 1
Case 2
Case 3
Case 4
LBO PinHigh
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
1101
1
010
0111
0
101
1000
1
Fourth Address
1
0010
0
(Linear Burst, LBO = Low)
Case 1
Case 2
Case 3
Case 4
LBO PinHigh
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0011
011
0
1101
100
1
0110
001
Fourth Address
1
1000
110
FUNCTION DESCRIPTION
The W2Z1M72SJ is an NBL SSRAM designed to sus-
tain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or
vice versa. All inputs (with the exception of OE, LBO
and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be inter-
nally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been de-
selected in order to load a new address for next opera-
tion.
Clock Enable (CKE) pin allows the operation of the chip
to be suspended as long as necessary. When CKE is
high, all synchronous inputs are ignored and the inter-
nal device registers will hold their previous values. NBL
SSRAM latches external address and initiates a cycle
when CKE and ADV are driven low at the rising edge of
the clock.
Output Enable (OE) can be used to disable the output
at any given time. Read operation is initiated when at
the rising edge of the clock, the address presented to
the address inputs are latched in the address register,
CKE is driven low, the write enable input signals WE
are driven high, and ADV driven low. The internal array
is read between the first rising edge and the second
rising edge of the clock and the data is latched in the
output register. At the second clock edge the data is
driven out of the SRAM. During read operation OE must
be driven low for the device to drive out the requested
data.
Write operation occurs when WE is driven low at the
rising edge of the clock. BW[d:a] can be used for byte
write operation. The pipe-lined NBL SSRAM uses a late-
late write cycle to utilize 100% of the bandwidth. At the
first rising edge of the clock, WE and address are reg-
istered, and the data associated with that address is
required two cycle later.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst seguence is provided by the external address.
The burst address counter wraps around to its initial
state upon completion. The burst sequence is deter-
mined by the state of the LBO pin. When this pin is low,
linear burst sequence is selected. And when this pin is
high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after 2 cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after 2 cycles of wake up time.
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