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參數(shù)資料
| 型號(hào)： | W29EE512-90 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 64K X 8 FLASH 5V PROM, 90 ns, PDIP32 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 152K |
| 代理商： | W29EE512-90 |
Preliminary W29EE512
- 11 -
Read Cycle Timing Parameters
(VCC = 5.0V
±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
W29EE512-70 W29EE512-90 W29EE512-12
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
TRC
70
-
90
-
120
-
nS
Chip Enable Access Time
TCE
-
70
-
90
-
120
nS
Address Access Time
TAA
-
70
-
90
-
120
nS
Output Enable Access Time
TOE
-35
-
40
-50
nS
CE High to High-Z Output
TCHZ
-25
-
25
-30
nS
OE High to High-Z Output
TOHZ
-25
-
25
-30
nS
Output Hold from Address Change
TOH
0-
0
-
0-
nS
Byte/Page-write Cycle Timing Parameters
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Write Cycle (Erase and Program)
TWC
--
10
mS
Address Setup Time
TAS
0-
-
nS
Address Hold Time
TAH
50
-
nS
WE and CE Setup Time
TCS
0-
-
nS
WE and CE Hold Time
TCH
0-
-
nS
OE High Setup Time
TOES
0-
-
nS
OE High Hold Time
TOEH
0-
-
nS
CE Pulse Width
TCP
90
-
nS
WE Pulse Width
TWP
90
-
nS
WE High Width
TWPH
100
-
nS
Data Setup Time
TDS
35
-
nS
Data Hold Time
TDH
0-
-
nS
Byte Load Cycle Time
TBLC
-
150
S
Notes: All AC timing signals observe the following guidelines for determining setup and hold times:
(1) High level signal's reference level is VIH.
(2) Low level signal's reference level is VIL.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W29EE512P-12 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 8 CMOS FLASH MEMORY |
| W29EE512P-12B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 8 CMOS FLASH MEMORY |
| W29EE512P-70 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 8 CMOS FLASH MEMORY |
| W29EE512P-70B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 8 CMOS FLASH MEMORY |
| W29EE512P-90 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 8 CMOS FLASH MEMORY |
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