參數(shù)資料
型號： W29D040CT55C
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 512K X 8 FLASH 5V PROM, 55 ns, PDSO32
封裝： TSOP-32
文件頁數(shù)： 36/40頁
文件大?。?/td> 280K
代理商： W29D040CT55C
W29D040C
Publication Release Date: January 1999
- 5 -
Revision A1
The manufacturer and device codes may also be read via the command register, for instances, when the
W29D040C is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in "Autoselet Codes".
Byte 0 (A0 = VIL) represents the manufacturer
′s code (Winbond = DAH) and byte 1 (A0 = VIH) the
device identifier code (W29D040C = 26). All identifiers for manufacturer and device will exhibit odd parity
with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Autoselect, A1 must be VIL.
The autoselect mode also facilitates the determination of sector protection in the system. By performing
a read operation at the address location XX02H with the higher order address bits A16
A18 set to the
desired sector address, the device will return 01H for a protected sector and 00H for a non-protected
sector.
Full Chip/Sector Protection
The W29D040C features hardware full chip/sector protection. This feature will disable both program and
erase operations in full chip or any combination of nineteen sectors of memory. The full chip sector
protect feature is enabled using programming equipment at the user
′s site. The device is shipped with all
sectors unprotected. (See "Device Bus Operations")
It is possible to determine if a sector is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02H, where the higher order address bits A16–A18
is the desired sector address, will produce a logical "1" at DQ0 for a protected sector.
DATA PROTECTION
The W29D040C is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific multi-
bus cycle command sequences. The device also incorporates several features to prevent inadvertent
write cycles resulting from VCC power-up and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, the W29D040C locks out write
cycles for VCC < VLKO (see DC Characteristics section for voltages). When VCC < VLKO, all internal
program/erase circuits are disabled, and the device resets to the read mode. The W29D040C ignores all
writes until VCC > VLKO. The user must ensure that the control pins are in the correct logic state when
VCC > VLKO to prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on OE, CE , or
WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or
WE = VIH. To initiate a write cycle
CE and
WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
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