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參數(shù)資料
| 型號： | W29D040C-55C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 512K X 8 FLASH 5V PROM, 55 ns, PDIP32 |
| 封裝： | PLASTIC, DIP-32 |
| 文件頁數(shù)： | 40/40頁 |
| 文件大?。?/td> | 280K |
| 代理商： | W29D040C-55C |
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W29D040C
Publication Release Date: January 1999
- 9 -
Revision A1
DQ7: Data Polling
The W29D040C device features Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed.
During the Embedded Program Algorithm, an attempt to read the device will produce the complement of
the data last written to DQ7. This DQ7 status also applies to programming during erase suspend. Upon
completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data
last written to DQ7.
During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7
output. Upon completion of the Embedded Erase Algorithm, or if the device enters the Erase Suspend
mode, an attempt to read the device will produce a "1" at the DQ7 output.
The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm".
For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six
WE write
pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
WE pulse. Data Polling must be performed at sector addresses within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while
the output enable (OE) is asserted low. This means that the device is driving status information on DQ7
at one instant of time and then that byte
′s valid data at the next instant of time. Depending on when the
system samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0–DQ6 may be
still invalid. The valid data on DQ0
DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out (see "Command Definitions").
See "
DATA Polling During Embedded Algorithm Timing Diagrams".
DQ6: Toggle Bit
The W29D040C also features the "Toggle Bit" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data
from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded
Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the
next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth
pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of
the sixth
WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the
last rising edge of the sector erase
WE pulse. The Toggle Bit is active during the sector erase time-out.
Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command
will cause DQ6 to toggle. See "Toggle Bit During Embedded Algorithm Timing Diagrams".
DQ5: Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count).
Under these conditions DQ5 will produce a "1" and DQ6 will stop toggling. This is a failure condition
which indicates that the program or erase cycle was not successfully completed. Data Polling is the
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