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參數(shù)資料
| 型號(hào)： | W27C02Q-70 |
| 英文描述： | EEPROM|256KX8|CMOS|TSSOP|32PIN|PLASTIC |
| 中文描述： | EEPROM的| 256KX8 |的CMOS | TSSOP封裝| 32腳|塑料 |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大?。?/td> | 184K |
| 代理商： | W27C02Q-70 |
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W27C01
128K
′
8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: April 15, 2002
- 1 -
Revision A2
GENERAL DESCRIPTION
The W27C01 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 131,072 x 8 bits.
It requires only one supply in the range of 5.0V
±
5% in
normal read mode. The W27C01 provides an electrical chip erase function.
FEATURES
Single power supply voltage:
5.0V
±
5%
High speed access time: 70 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current:
30 mA (max.)
Standby current: 20
μ
A (max.)
+12V erase/programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available
packages: 32-pin 600 mil DIP,
32-lead PLCC and 32-lead STSOP
PIN CONFIGURATIONS
A6
A5
A4
A3
A2
A1
A0
Q0
5
6
7
8
9
10
11
12
13
Q
1
Q
2
Q
4
Q
5
Q
6
1
4
4
3
2
1
3
2
3
1
3
0
A14
A8
A9
A11
29
28
27
26
25
24
23
22
21
32-lead PLCC
V
s
s
1
5
1
6
1
7
1
8
1
9
2
0
N
C
V
D
D
Q7
A
1
5
A
1
6
Q
3
A7
A
1
2
V
p
p
#
P
G
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
Q0
Q1
Q2
#OE
A10
#CE
Q7
Q6
Q5
Q4
Q3
VSS
32-lead STSOP
A15
A12
A7
A6
A5
A4
#PGM
V
DD
V
PP
A14
NC
A13
A8
A11
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Q0
A0
A2
A1
A3
A4
A5
A6
A7
A12
A15
A16
Vpp
Vss
Q2
Q1
30
29
31
32
25
24
26
27
28
20
21
22
23
19
18
17
Q5
#OE
A10
#CE
Q7
Q6
A13
A8
A9
A11
#PGM
NC
A14
Q3
Q4
V
DD
PDIP
BLOCK DIAGRAM
V
Vss
V
PP
DD
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
.
.
Q7
#CE
#OE
A0
.
.
A16
#PGM
PIN DESCRIPTION
SYMBOL
A0
A16
Q0
Q7
#CE
#OE
#PGM
V
PP
V
DD
V
ss
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
Ground
No Connection
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