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參數(shù)資料
| 型號： | W25Z040A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 128K×36bit Pipeline ZWS(Zero-Wait-State) SRAM(128K×36位無等待時間的管線CMOS同步靜態(tài)RAM) |
| 中文描述： | 128K的× 36bit管道ZWS（零等待狀態(tài)）的SRAM（128K的× 36位無等待時間的管線的CMOS同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 136K |
| 代理商： | W25Z040A |
W25Z040A
128K
×
36 PIPELINED ZWS SRAM
Publication Release Date: April 1999
- 1 -
Revision A2
GENERAL DESCRIPTION
The W25Z040A is a high-speed, low-power, Zero-Wait-State (ZWS) Synchronous Pipelined CMOS
Static RAM organized as 131,072
×
36 bits. A built-in two-bit burst address counter supports both
Linear and Interleaved burst mode. The mode to be executed is controlled by the
LBO
pin. A snooze
mode can reduce the power dissipation.
The ZWS SRAM is optimized for 100 percent bus utilization by eliminating wait states when
transitioning from read to write, or vice versa. All addresses, data inputs, clock enable (
CLKE
), write
enable (
WE
), byte-write enables (
BW
[4:1]) and chip enables (
CE1
, CE2 and
CE3
for easy depth
expansion) are synchronously sampled with by a positive-edge-triggered clock (CLK). Asynchronous
inputs include the output enable (OE), clock (CLK) and snooze (ZZ).
To provide 100 percent use of the data bus, the pipelined ZWS SRAM uses the two-stage write
address registers. For example, when the address and control signals are applied to the SRAM in
clock cycle one, the data associated with the address occurs two cycles later, or the clock cycle three.
The W25Z040A operates on a single 3.3V power supply, with all inputs and outputs compatible with
the LVTTL interface. Based on the bus efficiency, the device is ideal for high bandwidth application
systems.
FEATURES
Synchronous operation
High-speed access time: 3.8/4.2/4.5/5 nS
Single +3.3V power supply
Individual byte write capability
3.3V LVTTL compatible I/O
Clock-controlled and registered input
BLOCK DIAGRAM
Asynchronous output enable
Zero wait states between read/write cycles
Supports snooze mode (low-power state)
Internal burst counter supports Interleaved
burst mode & linear burst mode
Packaged in 100-pin TQFP
A0
:
A16
Add
Reg
Burst
Counter
Write
#0
128K X 36
Core Cell
Write
Data
#1
LBO
K1
A0, A1
Mux
Mux
Write
#0
Output
Write
#1
Output
Buffer
K
K
K
Read/Write Control
K
K
K1
CLK
OE
ADV/LD, WE, BW[4:1]
CLKE
CE1
CE2
CE3
I/O[36:1]
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