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參數(shù)資料
| 型號(hào)： | W25P010A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 32K×32 Burst Pipeline High-Speed CMOS Static RAM(32K×32位同步脈沖式管高速CMOS靜態(tài)RAM) |
| 中文描述： | 32K的管道爆裂× 32高速CMOS靜態(tài)RAM（32K的× 32位同步脈沖式管高速的CMOS靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大?。?/td> | 314K |
| 代理商： | W25P010A |
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W25P010A
Publication Release Date: September 1996
- 9 -
Revision A7
AC Timing Characteristics, continued
PARAMETER
SYM.
W25P010A-6
W25P010A-7
W25P010A-8
UNIT
NOTES
MIN.
0.5
MAX.
-
MIN.
0.5
MAX.
-
MIN.
0.5
MAX.
-
GW
,
BWE
X Hold Time
T
WH
nS
Clock Cycle Time
T
CYC
13.3
-
15
-
15
-
nS
Clock High Pulse Width
T
KH
5
-
6
-
6
-
nS
Clock Low Pulse Width
T
KL
5
-
6
-
6
-
nS
Clock to Output Valid
T
KQ
-
6
-
7
-
8
nS
Clock to Output High-Z
T
KHZ
2
13.3
2
15
2
15
nS
1, 5
15.3
26.6
17
30
17
30
nS
1, 6
Clock to Output Low-Z
T
KLZ
0
-
0
-
0
-
nS
1
Clock to Output Invalid
T
KX
2
-
2
-
2
-
nS
1, 5
15.3
-
17
-
17
-
nS
1, 6
Output Enable to Output Valid
T
OE
-
6
-
7
-
8
nS
Output Enable to Output High-
Z
T
OHZ
-
6
-
7
-
8
nS
1
Output Enable to Output Low-Z
T
OLZ
0
-
0
-
0
-
nS
1
Output Enable to Output Invalid
T
OX
0
-
0
-
0
-
nS
ZZ Standby Time
T
ZZS
-
100
-
100
-
100
nS
2
ZZ Recover Time
T
ZZR
100
-
100
-
100
-
nS
3
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.
4. Configuring signals LBO and FT are static and should not be changed during operations.
5. Output datas are not controlled by CE2, CE3 .
6. Output datas are controlled by CE2, CE3 .
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|---|---|
| W25P010AD-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| W25P010AD-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| W25P010AD-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| W25P010AF-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| W25P010AF-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
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