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參數(shù)資料
| 型號： | W256HT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 12 Output Buffer for 2 DDR and 3 SRAM DIMMS |
| 中文描述： | 256 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, SSOP-28 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 176K |
| 代理商： | W256HT |
W256
Document #: 38-07256 Rev. *C
Page 5 of 9
Switching Characteristics
[4]
Parameter
–
–
Name
Test Conditions
Min.
66
IN
DC
–5%
1.0
1.0
0.5
Typ.
Max.
180
IN
DC
+5%
Unit
MHz
%
Operating Frequency
Duty Cycle
[4,5]
= t
2
÷
t
1
Measured at 1.4V for 3.3V outputs
Measured at VDD/2 for 2.5V outputs.
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
Measured between 20% to 80% of
output (Refer to
Figure 1
)
Measured between 20% to 80% of
output (Refer to
Figure 1
)
All outputs equally loaded
All outputs equally loaded
t
3
t
4
t
3d
SDRAM Rising Edge Rate
[4]
SDRAM Falling Edge Rate
[4]
DDR Rising Edge Rate
[4]
2.50
2.50
1.50
V/ns
V/ns
V/ns
t
4d
DDR Falling Edge Rate
[4]
0.5
1.50
V/ns
t
5
t
6
Output to Output Skew
[4]
Output t4o Output Skew for
SDRAM
[2]
SDRAM Buffer HH Prop. Delay
[4]
SDRAM Buffer LLProp. Delay
[4]
100
150
ps
ps
t
7
t
8
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
5
5
10
10
ns
ns
Switching Waveforms
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.
Duty Cycle Timing
t
1
t
2
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.4V
2.4V
2.4V
0.4V
t
4
Output-Output Skew
t
5
OUTPUT
OUTPUT
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