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參數(shù)資料
| 型號(hào)： | W24L01AQ-12 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 12 ns, PDSO32 |
| 封裝： | 8 X 13.40 MM, TSOP1-32 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 208K |
| 代理商： | W24L01AQ-12 |
Preliminary W24L01A
- 6 -
Timing Waveforms, continued
Write Cycle 1 ( OE Clock)
Address
OE
CS1
CS2
WE
D
T
(1, 4)
OUT
IN
OHZ
WC
TWR1
TCW1
TCW2
TAW
TWP
TWR2
TAS
TDW
TDH
Write Cycle 2 ( OE = VIL Fixed)
Address
CS1
CS2
WE
D
T
(2)
(3)
T
WC
CW1
WR1
CW2
AW
WP
WR2
OW
WHZ (1, 4)
DW
DH
OH
AS
OUT
IN
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. Dout provides the read data for the next address.
4. Transition is measured
±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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