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參數(shù)資料
| 型號(hào)： | W245-30 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | W245-30 |
Frequency Multiplying, Peak Reducing EMI Solution
W245-30
Cypress Semiconductor Corporation
Document #: 38-07229 Rev. *B
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised August 13, 2002
0
Features
Cypress PREMIS family offering
Generates an EMI optimized clocking signal at the out-
put
Selectable output frequency range
Single 1.25%, 2.5%, 5% or 10% down or center spread
output
Integrated loop filter components
Operates with a 3.3 or 5V supply
Low power CMOS design
Available in 20-pin SSOP (Small Shrunk Outline Pack-
age)
Key Specifications
Supply Voltages:.........................................V
DD
= 3.3V±0.3V
or V
DD
= 5V±10%
Frequency range: ........................... 13 MHz < F
in
< 120 MHz
Cycle to Cycle Jitter: .........................................250 ps (max)
Output duty cycle: .................................40/60% (worst case)
W
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
X1
X2
AVDD
MW0^
SDATA
OR1^
SCLK
REFOUT
VDD
GND
IR1*
IR2*
SSOUT
MW1*
GND
14
13
15
11
12
VDD
MW2^
OR2*
SSON#^
GND
Simplified Block Diagram
Pin Configuration
SSOP
Spread Spectrum
Output
W245-30
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
W245-30
(EOutput
3.3V or 5.0V
Input
X1
X2
X1
SCLK
SDATA
SDATA
SCLK
IIC Interface
IIC Interface
Notes:
1.
Pins marked with ^ are internal pull-down resistors with
weak 250 k
.
Pins marked with * are internal pull-up resistors with weak
80 k
.
2.
[1, 2]
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