參數(shù)資料
型號(hào)： W24100Q-70LE
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： SRAM
英文描述： 128K X 8 STANDARD SRAM, 70 ns, PDSO32
封裝： 8 X 13.40 MM, TSOP1-32
文件頁(yè)數(shù)： 1/12頁(yè)
文件大?。?/td> 198K
代理商： W24100Q-70LE
W24100
128K
× 8 CMOS STATIC RAM
Publication Release Date: September 6, 2001
- 1 -
Revision A3
GENERAL DESCRIPTION
The W24100 is a normal-speed, very low-power CMOS static RAM organized as 131072
× 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
Low power consumption:
Active: 385 mW (max.)
Access time: 70 nS
Single 5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Package: 32-pin 600 mil DIP, 32-pin 450 mil
SOP, standard type one TSOP (8 mm
× 20
mm) and small type one TSOP (8 mm
× 13.4
mm)
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
#OE
A10
#CS1
I/O7
I/O6
I/O5
I/O4
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O8
A15
A12
A7
A6
A5
A4
V
CS2
#WE
A13
A8
DD
A11
A9
NC
A14
A16
VSS
I/O3
I/O2
I/O1
V
A8
A9
#WE
1
2
3
4
5
24
25
26
27
28
NC
A7
A6
A5
A12
A4
A3
A2
A1
6
7
8
9
20
21
22
23
A11
#OE
A10
#CS1
I/O8
I/O7
I/O6
I/O5
10
11
12
13
16
17
18
19
A0
I/O2
I/O3
I/O1
14
15
I/O4
A13
V
A14
A16
32
31
30
29
A15
CS2
DD
SS
32-pin
SOP
/
32-pin
DIP
BLOCK DIAGRAM
CORE CELL ARRAY
1024 ROWS
128 X 8 COLUMNS
DATA
CNTRL.
CLK
GEN.
R
O
W
D
E
C
O
D
E
R
A15
I/O CKT.
COLUMN DECODER
#WE
#OE
CLK GEN.
PRECHARGE CKT.
A13 A8 A1 A0 A11A10
#CS1
CS2
A16
A14
A12
A4
A3
A2
A7
A6
A5
A9
I/O1
I/O8
:
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
A16
Address Inputs
I/O1
I/O8
Data Inputs/Outputs
#CS1, CS2
Chip Select Input
#WE
Write Enable Input
#OE
Output Enable Input
VDD
Power Supply
VSS
Ground
NC
No Connection
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