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參數(shù)資料
| 型號(hào)： | W237 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 440BX/MX Spread Spectrum Frequency Synthesizer(440BX/MX寬頻譜頻率合成器) |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.240 INCH, TSSOP-48 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大?。?/td> | 216K |
| 代理商： | W237 |
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PRELIMINARY
440BX/MX Spread Spectrum Frequency Synthesizer
W237
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
January 7, 2000, rev. **
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Single-chip system frequency synthesizer for Mobile
Intel 440BX
Two copies of CPU output
I
2
C interface for programming
Seven copies of PCI output
Two 48/24MHz outputs for USB and SIO
Three buffered reference outputs
Eight buffered SDRAM outputs provide support for 2
DIMMs
Spread Spectrum feature enabled through I
2
C interface
and pin option
Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter:...........................................250 ps
CPU to CPU Output Skew:..........................................175 ps
PCI to PCI Output Skew:.............................................500 ps
VDDQ3:...................................................................3.3V±5%
VDDQ2:...................................................................2.5V±5%
SDRAM0:7 Delay: ...............................................+3.7 ns typ.
Notes:
1.
2.
Mode input latched at power-up.
Pin function with parentheses determined by MODE pin logic state. Internal 250-k
pull-up resistors present on inputs marked with *. Design should not rely
solely on internal resistor to set I/O pins HIGH.
Intel is a registered trademark of Intel Corporation.
I
C is a trademark of Philips Corporation.
Table 1. Clock Select Table
[1]
SEL100/66
(MHz)
CPU,SDRAM
(MHz)
PCI
(MHz)
0
66.6
33.3
1
100
33.3
Block Diagram
Pin Configuration
[2]
VDDQ3
REF0:2
VDDQ3
XTAL
OSC
PLL 1
X2
X1
SDRAM6/(CPU_STOP#)
SDRAM7/(PCI_ST0P#)
48/24MHz0
48/24MHz1
PLL2
VDDQ3
PCI_F
CPU0:1
SDRAM 0:5
FB
SCLK
SDATA
I/O PORT
Byte 0 - 5
Bit 0 - 7
I
2
C
{
SEL100/
66MHz#
SPREAD#
BUF_IN
PWR_DWN#
Control
Logic
MODE
Stop
VDDQ2
2
PCI0:5
Stop
÷2/÷3
6
Power
Down
Logic
REF1
REF0
GND
X1
X2
MODE
VDDQ3
PCI_F
PCI0
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
GND
*SEL100/66#
SDATA
I
2
C
SCLK
VDDQ3
48/24MHz0
48/24MHz1
GND
W
VDDQ3
SPREAD#
VDDQ3
REF2
PWR_DWN#*
GND
CPU0
CPU1
VDDQ2
BUF_IN
FB
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6/(CPU_STOP#)*
SDRAM7/(PCI_STOP#)*
VDDQ3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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