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參數(shù)資料
| 型號(hào)： | W182-5 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Full Feature Peak Reducing EMI Solution |
| 中文描述： | 全功能峰值抑制EMI解決方案 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 124K |
| 代理商： | W182-5 |
Full Feature Peak Reducing EMI Solution
W182
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
June 8, 2000, rev. *A
Features
Cypress PREMIS
family offering
Generates an EMI optimized clocking signal at the
output
Selectable output frequency range
Single 1.25% or 3.75% down or center spread output
Integrated loop filter components
Operates with a 3.3 or 5V supply
Low power CMOS design
Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ...........................................V
DD
= 3.3V±5%
or V
DD
= 5V±10%
Frequency Range: .............................. 8 MHz
≤
F
in
≤
28 MHz
Cycle to Cycle Jitter:........................................300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: ..................................5 ns (max.)
Table 1. Modulation Width Selection
SS%
W182
Output
W182-5
Output
0
F
in
≥
F
out
≥
F
in
– 1.25%
F
in
+ 0.625%
≥
F
in
≥
– 0.625%
1
F
in
≥
F
out
≥
F
in
– 3.75%
F
in
+ 1.875%
≥
F
in
≥
–1.875%
Table 2. Frequency Range Selection
FS2
FS1
Frequency Range
0
0
8 MHz
≤
F
IN
≤
10 MHz
10 MHz
≤
F
IN
≤
15 MHz
15 MHz
≤
F
IN
≤
18 MHz
18 MHz
≤
F
IN
≤
28 MHz
0
1
1
0
1
1
PREMIS is a trademark of Cypress Semiconductor Corporation.
Simplified Block Diagram
Pin Configuration
SOIC
Spread Spectrum
Output
W182
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
Output
W182
(EMI suppressed)
3.3V or 5.0V
XTAL
Input
X1
X2
W
14
13
12
11
10
1
2
3
4
5
6
7
FS2
CLKIN or X1
NC or X2
GND
GND
SS%
FS1
REFOUT
OE#
SSON#
Reset
VDD
VDD
CLKOUT
8
9
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